<s>
Pascal	B-General_Concept
is	O
the	O
codename	O
for	O
a	O
GPU	B-Architecture
microarchitecture	B-General_Concept
developed	O
by	O
Nvidia	O
,	O
as	O
the	O
successor	O
to	O
the	O
Maxwell	B-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
The	O
architecture	O
was	O
first	O
introduced	O
in	O
April	O
2016	O
with	O
the	O
release	O
of	O
the	O
Tesla	B-Device
P100	I-Device
(	O
GP100	O
)	O
on	O
April	O
5	O
,	O
2016	O
,	O
and	O
is	O
primarily	O
used	O
in	O
the	O
GeForce	B-Device
10	I-Device
series	I-Device
,	O
starting	O
with	O
the	O
GeForce	B-Device
GTX	I-Device
1080	I-Device
and	O
GTX	B-Device
1070	I-Device
(	O
both	O
using	O
the	O
GP104	B-Device
GPU	B-Architecture
)	O
,	O
which	O
were	O
released	O
on	O
May	O
17	O
,	O
2016	O
and	O
June	O
10	O
,	O
2016	O
respectively	O
.	O
</s>
<s>
Pascal	B-General_Concept
was	O
manufactured	O
using	O
TSMC	O
's	O
16	B-Algorithm
nm	I-Algorithm
FinFET	O
process	O
,	O
and	O
later	O
Samsung	B-Application
's	O
14nm	B-Algorithm
FinFET	O
process	O
.	O
</s>
<s>
The	O
architecture	O
is	O
named	O
after	O
the	O
17th	O
century	O
French	O
mathematician	O
and	O
physicist	O
,	O
Blaise	O
Pascal	B-General_Concept
.	O
</s>
<s>
In	O
April	O
2019	O
,	O
Nvidia	O
enabled	O
a	O
software	O
implementation	O
of	O
DirectX	B-Algorithm
Raytracing	I-Algorithm
on	O
Pascal-based	O
cards	O
starting	O
with	O
the	O
GTX	B-Device
1060	I-Device
6	O
GB	O
,	O
and	O
in	O
the	O
16	B-Device
series	I-Device
cards	O
,	O
a	O
feature	O
reserved	O
to	O
the	O
Turing-based	O
RTX	O
series	O
up	O
to	O
that	O
point	O
.	O
</s>
<s>
In	O
March	O
2014	O
,	O
Nvidia	O
announced	O
that	O
the	O
successor	O
to	O
Maxwell	B-General_Concept
would	O
be	O
the	O
Pascal	B-General_Concept
microarchitecture	I-General_Concept
;	O
announced	O
on	O
May	O
6	O
,	O
2016	O
and	O
released	O
on	O
May	O
27	O
of	O
the	O
same	O
year	O
.	O
</s>
<s>
The	O
Tesla	B-Device
P100	I-Device
(	O
GP100	O
chip	O
)	O
has	O
a	O
different	O
version	O
of	O
the	O
Pascal	B-General_Concept
architecture	O
compared	O
to	O
the	O
GTX	O
GPUs	B-Architecture
(	O
GP104	B-Device
chip	O
)	O
.	O
</s>
<s>
The	O
shader	O
units	O
in	O
GP104	B-Device
have	O
a	O
Maxwell-like	O
design	O
.	O
</s>
<s>
In	O
Pascal	B-General_Concept
,	O
an	O
SM	O
(	O
streaming	O
multiprocessor	O
)	O
consists	O
of	O
between	O
64-128	O
CUDA	B-Architecture
cores	O
,	O
depending	O
on	O
if	O
it	O
is	O
GP100	O
or	O
GP104	B-Device
.	O
</s>
<s>
Maxwell	B-General_Concept
packed	O
128	O
,	O
Kepler	B-General_Concept
192	O
,	O
Fermi	B-General_Concept
32	O
and	O
Tesla	B-Operating_System
only	O
8	O
CUDA	B-Architecture
cores	O
into	O
an	O
SM	O
;	O
the	O
GP100	O
SM	O
is	O
partitioned	O
into	O
two	O
processing	O
blocks	O
,	O
each	O
having	O
32	O
single-precision	O
CUDA	B-Architecture
Cores	O
,	O
an	O
instruction	O
buffer	O
,	O
a	O
warp	O
scheduler	O
,	O
2	O
texture	O
mapping	O
units	O
and	O
2	O
dispatch	O
units	O
.	O
</s>
<s>
CUDA	B-Architecture
Compute	O
Capability	O
6.0	O
.	O
</s>
<s>
Unified	O
memory	O
—	O
a	O
memory	O
architecture	O
,	O
where	O
the	O
CPU	O
and	O
GPU	B-Architecture
can	O
access	O
both	O
main	O
system	O
memory	O
and	O
memory	O
on	O
the	O
graphics	O
card	O
with	O
the	O
help	O
of	O
a	O
technology	O
called	O
"	O
Page	O
Migration	O
Engine	O
"	O
.	O
</s>
<s>
NVLink	O
—	O
a	O
high-bandwidth	O
bus	O
between	O
the	O
CPU	O
and	O
GPU	B-Architecture
,	O
and	O
between	O
multiple	O
GPUs	B-Architecture
.	O
</s>
<s>
More	O
registers	O
—	O
twice	O
the	O
amount	O
of	O
registers	O
per	O
CUDA	B-Architecture
core	O
compared	O
to	O
Maxwell	B-General_Concept
.	O
</s>
<s>
This	O
allows	O
the	O
scheduler	O
to	O
dynamically	O
adjust	O
the	O
amount	O
of	O
the	O
GPU	B-Architecture
assigned	O
to	O
multiple	O
tasks	O
,	O
ensuring	O
that	O
the	O
GPU	B-Architecture
remains	O
saturated	O
with	O
work	O
except	O
when	O
there	O
is	O
no	O
more	O
work	O
that	O
can	O
safely	O
be	O
distributed	O
to	O
distribute	O
.	O
</s>
<s>
Nvidia	O
therefore	O
has	O
safely	O
enabled	O
asynchronous	O
compute	O
in	O
Pascal	B-General_Concept
's	O
driver	O
.	O
</s>
<s>
Architectural	O
improvements	O
of	O
the	O
GP104	B-Device
architecture	O
include	O
the	O
following	O
:	O
</s>
<s>
CUDA	B-Architecture
Compute	O
Capability	O
6.1	O
.	O
</s>
<s>
DisplayPort	B-Protocol
1.4	O
,	O
HDMI	B-Protocol
2.0b	O
.	O
</s>
<s>
PureVideo	O
Feature	O
Set	O
H	O
hardware	O
video	O
decoding	O
HEVC	B-Algorithm
Main10(10bit )	O
,	O
Main12(12bit )	O
and	O
VP9	B-Algorithm
hardware	O
decoding	O
.	O
</s>
<s>
HDCP	B-Protocol
2.2	O
support	O
for	O
4K	O
DRM	O
protected	O
content	O
playback	O
and	O
streaming	O
(	O
Maxwell	B-General_Concept
GM200	O
and	O
GM204	O
lack	O
HDCP	B-Protocol
2.2	O
support	O
,	O
GM206	O
supports	O
HDCP	B-Protocol
2.2	O
)	O
.	O
</s>
<s>
NVENC	B-General_Concept
HEVC	B-Algorithm
Main10	O
10bit	O
hardware	O
encoding	O
.	O
</s>
<s>
GPU	B-Architecture
Boost	O
3.0	O
.	O
</s>
<s>
A	O
chip	O
is	O
partitioned	O
into	O
Graphics	B-Architecture
Processor	I-Architecture
Clusters	O
(	O
GPCs	O
)	O
.	O
</s>
<s>
For	O
the	O
GP104	B-Device
chips	O
,	O
a	O
GPC	O
encompasses	O
5	O
SMs	O
.	O
</s>
<s>
An	O
SMP	O
encompasses	O
128	O
single-precision	O
ALUs	O
(	O
"	O
CUDA	B-Architecture
cores	O
"	O
)	O
on	O
GP104	B-Device
chips	O
and	O
64	O
single-precision	O
ALUs	O
on	O
GP100	O
chips	O
.	O
</s>
<s>
4	O
SIMD	O
Vector	O
Units	O
(	O
each	O
16-lane	O
wide	O
)	O
=	O
64	O
)	O
,	O
Nvidia	O
(	O
regularly	O
calling	O
shader	O
processors	O
"	O
CUDA	B-Architecture
cores	O
"	O
)	O
experimented	O
with	O
very	O
different	O
numbers	O
:	O
</s>
<s>
On	O
Pascal	B-General_Concept
it	O
depends	O
:	O
</s>
<s>
On	O
the	O
GP104	B-Device
1	O
SM	O
combines	O
128	O
single-precision	O
ALUs	O
,	O
4	O
double-precision	O
ALUs	O
providing	O
a	O
32:1	O
ratio	O
,	O
and	O
one	O
half-precision	O
ALU	O
that	O
contains	O
a	O
vector	O
of	O
two	O
half-precision	O
floats	O
which	O
can	O
execute	O
the	O
same	O
instruction	O
on	O
both	O
floats	O
providing	O
a	O
64:1	O
ratio	O
if	O
the	O
same	O
instruction	O
is	O
used	O
on	O
both	O
elements	O
.	O
</s>
<s>
The	O
Polymorph	O
Engine	O
version	O
4.0	O
is	O
the	O
unit	O
responsible	O
for	O
Tessellation	B-Algorithm
.	O
</s>
<s>
GP100	O
:	O
Nvidia	B-Device
Tesla	I-Device
P100	O
GPU	B-Architecture
accelerator	O
is	O
targeted	O
at	O
GPGPU	B-Architecture
applications	O
such	O
as	O
FP64	O
double	O
precision	O
compute	O
and	O
deep	O
learning	O
training	O
that	O
uses	O
FP16	O
.	O
</s>
<s>
Quadro	B-Application
GP100	O
also	O
uses	O
the	O
GP100	O
GPU	B-Architecture
.	O
</s>
<s>
GP102	O
:	O
This	O
GPU	B-Architecture
is	O
used	O
in	O
the	O
TITAN	B-Device
Xp	I-Device
,	O
Titan	B-Device
X	I-Device
and	O
the	O
GeForce	B-Device
GTX	I-Device
1080	I-Device
Ti	I-Device
.	O
</s>
<s>
It	O
is	O
also	O
used	O
in	O
the	O
Quadro	B-Application
P6000	O
&	O
Tesla	B-Operating_System
P40	O
.	O
</s>
<s>
GP104	B-Device
:	O
This	O
GPU	B-Architecture
is	O
used	O
in	O
the	O
GeForce	B-Device
GTX	I-Device
1070	I-Device
,	O
GTX	B-Device
1070	I-Device
Ti	I-Device
and	O
the	O
GTX	B-Device
1080	I-Device
.	O
</s>
<s>
The	O
GTX	B-Device
1070	I-Device
has	O
15/20	O
and	O
the	O
GTX	B-Device
1070	I-Device
Ti	I-Device
has	O
19/20	O
of	O
its	O
SMs	O
enabled	O
.	O
</s>
<s>
Both	O
are	O
connected	O
to	O
GDDR5	O
memory	O
,	O
while	O
the	O
GTX	B-Device
1080	I-Device
is	O
a	O
full	O
chip	O
and	O
is	O
connected	O
to	O
GDDR5X	O
memory	O
.	O
</s>
<s>
It	O
is	O
also	O
used	O
in	O
the	O
Quadro	B-Application
P5000	O
,	O
Quadro	B-Application
P4000	O
and	O
Tesla	B-Device
P4	I-Device
.	O
</s>
<s>
GP106	O
:	O
This	O
GPU	B-Architecture
is	O
used	O
in	O
the	O
GeForce	B-Device
GTX	I-Device
1060	I-Device
with	O
GDDR5/GDDR5X	O
memory	O
.	O
</s>
<s>
It	O
is	O
also	O
used	O
in	O
the	O
Quadro	B-Application
P2000	O
.	O
</s>
<s>
GP107	O
:	O
This	O
GPU	B-Architecture
is	O
used	O
in	O
the	O
GeForce	B-Device
GTX	I-Device
1050	I-Device
Ti	O
and	O
GeForce	B-Device
GTX	I-Device
1050	I-Device
.	O
</s>
<s>
It	O
is	O
also	O
used	O
in	O
the	O
Quadro	B-Application
P1000	O
,	O
Quadro	B-Application
P600	O
,	O
Quadro	B-Application
P620	O
&	O
Quadro	B-Application
P400	O
.	O
</s>
<s>
GP108	O
:	O
This	O
GPU	B-Architecture
is	O
used	O
in	O
the	O
GeForce	O
GT	O
1010	O
and	O
GeForce	B-Device
GT	I-Device
1030	I-Device
.	O
</s>
<s>
On	O
the	O
GP104	B-Device
chip	O
an	O
SM	O
consists	O
of	O
128	O
single-precision	O
ALUs	O
(	O
"	O
CUDA	B-Architecture
cores	O
"	O
)	O
,	O
on	O
the	O
GP100	O
of	O
64	O
single-precision	O
ALUs	O
.	O
</s>
<s>
Due	O
to	O
different	O
organization	O
of	O
the	O
chips	O
,	O
like	O
number	O
of	O
double	O
precision	O
ALUs	O
,	O
the	O
theoretical	O
double	O
precision	O
performance	O
of	O
the	O
GP100	O
is	O
half	O
of	O
the	O
theoretical	O
one	O
for	O
single	O
precision	O
;	O
the	O
ratio	O
is	O
1/32	O
for	O
the	O
GP104	B-Device
chip	O
.	O
</s>
<s>
The	O
theoretical	O
single-precision	O
processing	O
power	O
of	O
a	O
Pascal	B-General_Concept
GPU	B-Architecture
in	O
GFLOPS	O
is	O
computed	O
as	O
2	O
X	O
(	O
operations	O
per	O
FMA	O
instruction	O
per	O
CUDA	B-Architecture
core	O
per	O
cycle	O
)	O
×	O
number	O
of	O
CUDA	B-Architecture
cores	O
×	O
core	O
clock	O
speed	O
(	O
in	O
GHz	O
)	O
.	O
</s>
<s>
The	O
theoretical	O
double-precision	O
processing	O
power	O
of	O
a	O
Pascal	B-General_Concept
GPU	B-Architecture
is	O
1/2	O
of	O
the	O
single	O
precision	O
performance	O
on	O
Nvidia	O
GP100	O
,	O
and	O
1/32	O
of	O
Nvidia	O
GP102	O
,	O
GP104	B-Device
,	O
GP106	O
,	O
GP107	O
&	O
GP108	O
.	O
</s>
<s>
The	O
theoretical	O
half-precision	O
processing	O
power	O
of	O
a	O
Pascal	B-General_Concept
GPU	B-Architecture
is	O
2×	O
of	O
the	O
single	O
precision	O
performance	O
on	O
GP100	O
and	O
1/64	O
on	O
GP104	B-Device
,	O
GP106	O
,	O
GP107	O
&	O
GP108	O
.	O
</s>
<s>
The	O
Pascal	B-General_Concept
architecture	O
was	O
succeeded	O
in	O
2017	O
by	O
Volta	B-General_Concept
in	O
the	O
HPC	B-Architecture
,	O
cloud	B-Architecture
computing	I-Architecture
,	O
and	O
self-driving	O
car	O
markets	O
,	O
and	O
in	O
2018	O
by	O
Turing	O
in	O
the	O
consumer	O
and	O
business	O
market	O
.	O
</s>
