<s>
In	O
computer	B-General_Concept
science	I-General_Concept
,	O
a	O
parallel	B-Operating_System
random-access	I-Operating_System
machine	I-Operating_System
(	O
parallel	B-Operating_System
RAM	I-Operating_System
or	O
PRAM	O
)	O
is	O
a	O
shared-memory	B-Operating_System
abstract	B-Application
machine	I-Application
.	O
</s>
<s>
As	O
its	O
name	O
indicates	O
,	O
the	O
PRAM	O
is	O
intended	O
as	O
the	O
parallel-computing	O
analogy	O
to	O
the	O
random-access	B-Application
machine	I-Application
(	O
RAM	B-Architecture
)	O
(	O
not	O
to	O
be	O
confused	O
with	O
random-access	B-Architecture
memory	I-Architecture
)	O
.	O
</s>
<s>
In	O
the	O
same	O
way	O
that	O
the	O
RAM	B-Architecture
is	O
used	O
by	O
sequential-algorithm	O
designers	O
to	O
model	O
algorithmic	O
performance	O
(	O
such	O
as	O
time	O
complexity	O
)	O
,	O
the	O
PRAM	O
is	O
used	O
by	O
parallel-algorithm	O
designers	O
to	O
model	O
parallel	O
algorithmic	O
performance	O
(	O
such	O
as	O
time	O
complexity	O
,	O
where	O
the	O
number	O
of	O
processors	O
assumed	O
is	O
typically	O
also	O
stated	O
)	O
.	O
</s>
<s>
Similar	O
to	O
the	O
way	O
in	O
which	O
the	O
RAM	B-Application
model	I-Application
neglects	O
practical	O
issues	O
,	O
such	O
as	O
access	O
time	O
to	O
cache	O
memory	O
versus	O
main	O
memory	O
,	O
the	O
PRAM	O
model	O
neglects	O
such	O
issues	O
as	O
synchronization	O
and	O
communication	O
,	O
but	O
provides	O
any	O
(	O
problem-size-dependent	O
)	O
number	O
of	O
processors	O
.	O
</s>
<s>
Read/write	O
conflicts	O
,	O
commonly	O
termed	O
interlocking	O
in	O
accessing	O
the	O
same	O
shared	B-Operating_System
memory	I-Operating_System
location	O
simultaneously	O
are	O
resolved	O
by	O
one	O
of	O
the	O
following	O
strategies	O
:	O
</s>
<s>
Concurrent	B-Operating_System
read	I-Operating_System
concurrent	I-Operating_System
write	I-Operating_System
(	O
CRCW	B-Operating_System
)	O
—	O
multiple	O
processors	O
can	O
read	O
and	O
write	O
.	O
</s>
<s>
A	O
CRCW	B-Operating_System
PRAM	I-Operating_System
is	O
sometimes	O
called	O
a	O
concurrent	O
random-access	B-Application
machine	I-Application
.	O
</s>
<s>
There	O
is	O
no	O
limit	O
on	O
the	O
amount	O
of	O
shared	B-Operating_System
memory	I-Operating_System
in	O
the	O
system	O
.	O
</s>
<s>
Resource	B-General_Concept
contention	I-General_Concept
is	O
absent	O
.	O
</s>
<s>
The	O
programs	O
written	O
on	O
these	O
machines	O
are	O
,	O
in	O
general	O
,	O
of	O
type	O
SIMD	B-Device
.	O
</s>
<s>
These	O
kinds	O
of	O
algorithms	O
are	O
useful	O
for	O
understanding	O
the	O
exploitation	O
of	O
concurrency	B-Application
,	O
dividing	O
the	O
original	O
problem	O
into	O
similar	O
sub-problems	O
and	O
solving	O
them	O
in	O
parallel	O
.	O
</s>
<s>
The	O
introduction	O
of	O
the	O
formal	O
'	O
P-RAM	O
'	O
model	O
in	O
Wyllie	O
's	O
1979	O
thesis	O
had	O
the	O
aim	O
of	O
quantifying	O
analysis	B-Operating_System
of	I-Operating_System
parallel	I-Operating_System
algorithms	I-Operating_System
in	O
a	O
way	O
analogous	O
to	O
the	B-Architecture
Turing	I-Architecture
Machine	I-Architecture
.	O
</s>
<s>
The	O
analysis	O
focused	O
on	O
a	O
MIMD	O
model	O
of	O
programming	O
using	O
a	O
CREW	O
model	O
but	O
showed	O
that	O
many	O
variants	O
,	O
including	O
implementing	O
a	O
CRCW	B-Operating_System
model	O
and	O
implementing	O
on	O
an	O
SIMD	B-Device
machine	O
,	O
were	O
possible	O
with	O
only	O
constant	O
overhead	O
.	O
</s>
<s>
PRAM	O
algorithms	O
cannot	O
be	O
parallelized	O
with	O
the	O
combination	O
of	O
CPU	B-General_Concept
and	O
dynamic	O
random-access	B-Architecture
memory	I-Architecture
(	O
DRAM	O
)	O
because	O
DRAM	O
does	O
not	O
allow	O
concurrent	O
access	O
to	O
a	O
single	O
bank	O
(	O
not	O
even	O
different	O
addresses	O
in	O
the	O
bank	O
)	O
;	O
but	O
they	O
can	O
be	O
implemented	O
in	O
hardware	O
or	O
read/write	O
to	O
the	O
internal	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
(	O
SRAM	O
)	O
blocks	O
of	O
a	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
(	O
FPGA	B-Architecture
)	O
,	O
it	O
can	O
be	O
done	O
using	O
a	O
CRCW	B-Operating_System
algorithm	O
.	O
</s>
<s>
However	O
,	O
the	O
test	O
for	O
practical	O
relevance	O
of	O
PRAM	O
(	O
or	O
RAM	B-Architecture
)	O
algorithms	O
depends	O
on	O
whether	O
their	O
cost	O
model	O
provides	O
an	O
effective	O
abstraction	O
of	O
some	O
computer	O
;	O
the	O
structure	O
of	O
that	O
computer	O
can	O
be	O
quite	O
different	O
than	O
the	O
abstract	O
model	O
.	O
</s>
<s>
But	O
,	O
articles	O
such	O
as	O
demonstrate	O
how	O
a	O
PRAM-like	O
abstraction	O
can	O
be	O
supported	O
by	O
the	O
explicit	B-Operating_System
multi-threading	I-Operating_System
(	O
XMT	O
)	O
paradigm	O
and	O
articles	O
such	O
as	O
demonstrate	O
that	O
a	O
PRAM	O
algorithm	O
for	O
the	O
maximum	B-Algorithm
flow	I-Algorithm
problem	I-Algorithm
can	O
provide	O
strong	O
speedups	O
relative	O
to	O
the	O
fastest	O
serial	O
program	O
for	O
the	O
same	O
problem	O
.	O
</s>
<s>
This	O
is	O
an	O
example	O
of	O
SystemVerilog	B-Language
code	O
which	O
finds	O
the	O
maximum	O
value	O
in	O
the	O
array	O
in	O
only	O
2	O
clock	O
cycles	O
.	O
</s>
<s>
It	O
uses	O
CRCW	B-Operating_System
memory	O
;	O
m[i]	O
<=	O
1	O
and	O
maxNo	O
<=	O
data[i]	O
are	O
written	O
concurrently	O
.	O
</s>
<s>
The	O
concurrency	B-Application
causes	O
no	O
conflicts	O
because	O
the	O
algorithm	O
guarantees	O
that	O
the	O
same	O
value	O
is	O
written	O
to	O
the	O
same	O
memory	O
.	O
</s>
<s>
This	O
code	O
can	O
be	O
run	O
on	O
FPGA	B-Architecture
hardware	O
.	O
</s>
