<s>
Package	B-Algorithm
on	I-Algorithm
a	I-Algorithm
package	I-Algorithm
(	O
PoP	O
)	O
is	O
an	O
integrated	B-Algorithm
circuit	I-Algorithm
packaging	I-Algorithm
method	O
to	O
vertically	O
combine	O
discrete	O
logic	O
and	O
memory	O
ball	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
BGA	O
)	O
packages	O
.	O
</s>
<s>
This	O
allows	O
higher	O
component	O
density	O
in	O
devices	O
,	O
such	O
as	O
mobile	O
phones	O
,	O
personal	B-Application
digital	I-Application
assistants	I-Application
(	O
PDA	B-Application
)	O
,	O
and	O
digital	B-Device
cameras	I-Device
,	O
at	O
the	O
cost	O
of	O
slightly	O
higher	O
height	O
requirements	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
bottom	O
could	O
be	O
a	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
(	O
SoC	B-Architecture
)	O
for	O
a	O
mobile	O
phone	O
.	O
</s>
<s>
The	O
package	B-Algorithm
on	I-Algorithm
a	I-Algorithm
package	I-Algorithm
technique	O
tries	O
to	O
combine	O
the	O
benefits	O
of	O
traditional	O
packaging	B-Algorithm
with	O
the	O
benefits	O
of	O
die-stacking	B-Architecture
techniques	O
,	O
while	O
avoiding	O
their	O
drawbacks	O
.	O
</s>
<s>
Traditional	O
packaging	B-Algorithm
places	O
each	O
die	O
in	O
its	O
own	O
package	O
,	O
a	O
package	O
designed	O
for	O
normal	O
PCB	O
assembly	O
techniques	O
that	O
place	O
each	O
package	O
directly	O
on	O
the	O
PCB	O
side-by-side	O
.	O
</s>
<s>
The	O
3D	B-Architecture
die-stacking	I-Architecture
system	B-Algorithm
in	I-Algorithm
package	I-Algorithm
(	O
SiP	O
)	O
techniques	O
stacks	O
multiple	O
die	O
in	O
a	O
single	O
package	O
,	O
which	O
has	O
several	O
advantages	O
and	O
also	O
some	O
disadvantages	O
compared	O
to	O
traditional	O
PCB	O
assembly	O
.	O
</s>
<s>
In	O
embedded	B-Architecture
PoP	O
techniques	O
,	O
chips	O
are	O
embedded	B-Architecture
in	O
a	O
substrate	O
on	O
the	O
bottom	O
of	O
the	O
package	O
.	O
</s>
<s>
The	O
main	O
financial	O
benefit	O
of	O
package	B-Algorithm
on	I-Algorithm
a	I-Algorithm
package	I-Algorithm
is	O
that	O
the	O
memory	O
device	O
is	O
decoupled	O
from	O
the	O
logic	O
device	O
.	O
</s>
<s>
Therefore	O
this	O
gives	O
PoP	O
all	O
the	O
same	O
advantages	O
that	O
traditional	O
packaging	B-Algorithm
has	O
over	O
stacked-die	O
products	O
:	O
</s>
<s>
The	O
end	O
user	O
(	O
such	O
as	O
makers	O
of	O
mobile	O
phones	O
or	O
digital	B-Device
cameras	I-Device
)	O
controls	O
the	O
logistics	O
.	O
</s>
<s>
Package	B-Algorithm
on	I-Algorithm
a	I-Algorithm
package	I-Algorithm
is	O
also	O
known	O
by	O
other	O
names	O
:	O
</s>
<s>
In	O
2001	O
,	O
a	O
Toshiba	O
research	O
team	O
including	O
T	O
.	O
Imoto	O
,	O
M	O
.	O
Matsui	O
and	O
C	O
.	O
Takubo	O
developed	O
a	O
"	O
System	O
Block	O
Module	O
"	O
wafer	O
bonding	O
process	O
for	O
manufacturing	O
3D	B-Architecture
integrated	I-Architecture
circuit	I-Architecture
(	O
3D	B-Architecture
IC	I-Architecture
)	O
packages	O
.	O
</s>
<s>
The	O
earliest	O
known	O
commercial	O
use	O
of	O
a	O
3D	O
package-on-package	O
chip	O
was	O
in	O
Sony	B-Operating_System
's	I-Operating_System
PlayStation	I-Operating_System
Portable	I-Operating_System
(	O
PSP	B-Operating_System
)	O
handheld	B-Application
game	I-Application
console	I-Application
,	O
released	O
in	O
2004	O
.	O
</s>
<s>
The	O
PSP	B-Device
hardware	I-Device
includes	O
eDRAM	O
(	O
embedded	B-Architecture
DRAM	O
)	O
memory	O
manufactured	O
by	O
Toshiba	O
in	O
a	O
3D	O
package	O
chip	O
with	O
two	O
dies	O
stacked	O
vertically	O
.	O
</s>
<s>
Toshiba	O
called	O
it	O
"	O
semi-embedded	O
DRAM	O
"	O
at	O
the	O
time	O
,	O
before	O
later	O
calling	O
it	O
a	O
stacked	O
"	O
chip-on-chip	O
"	O
(	O
CoC	O
)	O
solution	O
.	O
</s>
<s>
In	O
April	O
2007	O
,	O
Toshiba	O
commercialized	O
an	O
eight-layer	O
3D	B-Architecture
chip	I-Architecture
package	O
,	O
the	O
16GB	O
THGAM	O
embedded	B-Architecture
NAND	O
flash	O
memory	O
chip	O
,	O
which	O
was	O
manufactured	O
with	O
eight	O
stacked	O
2GB	O
NAND	O
flash	O
chips	O
.	O
</s>
<s>
In	O
September	O
2007	O
,	O
Hynix	O
Semiconductor	O
introduced	O
24-layer	O
3D	O
packaging	B-Algorithm
technology	O
,	O
with	O
a	O
16GB	O
flash	O
memory	O
chip	O
that	O
was	O
manufactured	O
with	O
24	O
stacked	O
NAND	O
flash	O
chips	O
using	O
a	O
wafer	O
bonding	O
process	O
.	O
</s>
