<s>
POWER9	B-Device
is	O
a	O
family	O
of	O
superscalar	B-General_Concept
,	O
multithreading	B-General_Concept
,	O
multi-core	B-Architecture
microprocessors	B-Architecture
produced	O
by	O
IBM	O
,	O
based	O
on	O
the	O
Power	B-Architecture
ISA	I-Architecture
.	O
</s>
<s>
The	O
POWER9-based	O
processors	O
are	O
being	O
manufactured	O
using	O
a	O
14	O
nm	O
FinFET	O
process	O
,	O
in	O
12	O
-	O
and	O
24-core	O
versions	O
,	O
for	O
scale	O
out	O
and	O
scale	O
up	O
applications	O
,	O
and	O
possibly	O
other	O
variations	O
,	O
since	O
the	O
POWER9	B-Device
architecture	O
is	O
open	O
for	O
licensing	O
and	O
modification	O
by	O
the	O
OpenPOWER	B-Application
Foundation	I-Application
members	O
.	O
</s>
<s>
Summit	B-Device
,	O
the	O
fourth	O
fastest	O
supercomputer	O
in	O
the	O
world	O
(	O
based	O
on	O
the	O
Top500	O
list	O
as	O
of	O
June	O
2022	O
)	O
,	O
is	O
based	O
on	O
POWER9	B-Device
,	O
while	O
also	O
using	O
Nvidia	B-Device
Tesla	I-Device
GPUs	B-Architecture
as	O
accelerators	O
.	O
</s>
<s>
The	O
POWER9	B-Device
core	O
comes	O
in	O
two	O
variants	O
,	O
a	O
four-way	O
multithreaded	B-Operating_System
one	O
called	O
SMT4	O
and	O
an	O
eight-way	O
one	O
called	O
SMT8	O
.	O
</s>
<s>
The	O
result	O
is	O
that	O
the	O
12-core	O
and	O
24-core	O
versions	O
of	O
POWER9	B-Device
each	O
consist	O
of	O
the	O
same	O
number	O
of	O
slices	O
(	O
96	O
each	O
)	O
and	O
the	O
same	O
amount	O
of	O
L1cache	O
.	O
</s>
<s>
A	O
POWER9	B-Device
core	O
,	O
whether	O
SMT4	O
or	O
SMT8	O
,	O
has	O
a	O
12-stage	O
pipeline	O
(	O
five	O
stages	O
shorter	O
than	O
its	O
predecessor	O
,	O
the	O
POWER8	B-Device
)	O
,	O
but	O
aims	O
to	O
retain	O
the	O
clock	O
frequency	O
of	O
around	O
4GHz	O
.	O
</s>
<s>
It	O
will	O
be	O
the	O
first	O
to	O
incorporate	O
elements	O
of	O
the	O
Power	B-Architecture
ISA	I-Architecture
v.3.0	O
that	O
was	O
released	O
in	O
December	O
2015	O
,	O
including	O
the	O
VSX-3	O
instructions	O
.	O
</s>
<s>
The	O
POWER9	B-Device
design	O
is	O
made	O
to	O
be	O
modular	O
and	O
used	O
in	O
more	O
processor	O
variants	O
and	O
used	O
for	O
licensing	O
,	O
on	O
a	O
different	O
fabrication	O
process	O
than	O
IBM	O
's	O
.	O
</s>
<s>
The	O
POWER9	B-Device
comes	O
with	O
a	O
new	O
interrupt	O
controller	O
architecture	O
called	O
"	O
eXternal	O
Interrupt	O
Virtualization	O
Engine	O
"	O
(	O
XIVE	O
)	O
which	O
replaces	O
a	O
much	O
simpler	O
architecture	O
that	O
was	O
used	O
in	O
POWER4	O
through	O
POWER8	B-Device
.	O
</s>
<s>
XIVE	O
will	O
also	O
be	O
used	O
in	O
Power10	B-Operating_System
.	O
</s>
<s>
Both	O
POWER9	B-Device
variants	O
can	O
ship	O
in	O
versions	O
with	O
some	O
cores	O
disabled	O
due	O
to	O
yield	O
reasons	O
,	O
as	O
such	O
Raptor	O
Computing	O
Systems	O
first	O
sold	O
4-core	O
chips	O
,	O
and	O
even	O
IBM	O
initially	O
sold	O
its	O
AC922	O
systems	O
with	O
no	O
more	O
than	O
22-core	O
chips	O
,	O
even	O
though	O
both	O
types	O
of	O
chips	O
have	O
24	O
cores	O
on	O
their	O
dies	O
.	O
</s>
<s>
A	O
lot	O
of	O
facilities	O
are	O
on-chip	O
for	O
helping	O
with	O
massive	O
off-chip	O
I/O	B-General_Concept
performance	O
:	O
</s>
<s>
The	O
SO	O
variant	O
has	O
integrated	O
DDR4	O
controllers	O
for	O
directly	O
attached	O
RAM	O
,	O
while	O
the	O
SU	O
variant	O
will	O
use	O
the	O
off-chip	O
Centaur	O
architecture	O
introduced	O
with	O
POWER8	B-Device
to	O
include	O
high	O
performance	O
eDRAM	O
L4	O
cache	O
and	O
memory	O
controllers	O
for	O
DDR4	O
RAM	O
.	O
</s>
<s>
General	O
purpose	O
PCIe	O
v.4	O
connections	O
for	O
attaching	O
regular	O
ASICs	O
,	O
FPGAs	B-Architecture
and	O
other	O
peripherals	O
as	O
well	O
as	O
CAPI	O
2.0	O
and	O
CAPI	O
1.0	O
devices	O
designed	O
for	O
POWER8	B-Device
.	O
</s>
<s>
Multiprocessor	O
(	O
symmetric	B-Operating_System
multiprocessor	I-Operating_System
system	I-Operating_System
)	O
links	O
to	O
connect	O
other	O
POWER9	B-Device
processors	O
on	O
the	O
same	O
motherboard	O
,	O
or	O
in	O
other	O
closely	O
attached	O
enclosures	O
.	O
</s>
<s>
POWER9	B-Device
chips	O
can	O
be	O
made	O
with	O
two	O
types	O
of	O
cores	O
,	O
and	O
in	O
a	O
Scale	O
Out	O
or	O
Scale	O
Up	O
configuration	O
.	O
</s>
<s>
POWER9	B-Device
cores	O
are	O
either	O
SMT4	O
or	O
SMT8	O
,	O
with	O
SMT8	O
cores	O
intended	O
for	O
PowerVM	B-Application
systems	O
,	O
while	O
the	O
SMT4	O
cores	O
are	O
intended	O
for	O
PowerNV	O
systems	O
,	O
which	O
do	O
not	O
use	O
PowerVM	B-Application
,	O
and	O
predominantly	O
run	O
Linux	B-Application
.	O
</s>
<s>
With	O
POWER9	B-Device
,	O
chips	O
made	O
for	O
Scale	O
Out	O
can	O
support	O
directly-attached	O
memory	O
,	O
while	O
Scale	O
Up	O
chips	O
are	O
intended	O
for	O
use	O
with	O
machines	O
with	O
more	O
than	O
two	O
CPU	B-General_Concept
sockets	I-General_Concept
,	O
and	O
use	O
buffered	O
memory	O
.	O
</s>
<s>
The	O
IBM	O
Portal	O
for	O
OpenPOWER	B-Application
lists	O
the	O
three	O
available	O
modules	O
for	O
the	O
Nimbus	O
chip	O
,	O
although	O
the	O
Scale-Out	O
SMT8	O
variant	O
for	O
PowerVM	B-Application
also	O
uses	O
the	O
LaGrange	O
module/socket	O
:	O
</s>
<s>
Sforza	O
modules	O
use	O
a	O
land	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
LGA	O
)	O
2601-pin	O
socket	O
.	O
</s>
<s>
Talos	O
II	O
–	O
two-socket	O
workstation/server	O
platform	O
using	O
POWER9	B-Device
SMT4	O
Sforza	O
processors	O
;	O
available	O
as	O
2U	O
server	O
,	O
4U	O
server	O
,	O
tower	O
,	O
or	O
EATX	O
mainboard	O
.	O
</s>
<s>
Marketed	O
as	O
secure	O
and	O
owner-controllable	O
with	O
free	B-Application
and	O
open-source	B-Application
software	I-Application
and	O
firmware	O
.	O
</s>
<s>
Power	O
System	O
AC922	O
–	O
2U	O
,	O
2×	O
POWER9	B-Device
SMT4	O
Monza	O
,	O
with	O
up	O
to	O
6×	O
Nvidia	B-General_Concept
Volta	I-General_Concept
GPUs	B-Architecture
,	O
2×	O
CAPI	O
2.0	O
attached	O
accelerators	O
and	O
1	O
TiB	O
DDR4	O
RAM	O
.	O
</s>
<s>
Power	O
System	O
L922	O
–	O
2U	O
,	O
1	O
–	O
2×	O
POWER9	B-Device
SMT8	O
,	O
8	O
–	O
12	O
cores	O
per	O
processor	O
,	O
up	O
to	O
4	O
TiB	O
DDR4	O
RAM	O
(	O
1	O
TiB	O
=	O
1024	O
GiB	O
)	O
,	O
PowerVM	B-Application
running	O
Linux	B-Application
.	O
</s>
<s>
Power	O
System	O
S914	O
–	O
4U	O
,	O
1×	O
POWER9	B-Device
SMT8	O
,	O
4	O
–	O
8	O
cores	O
,	O
up	O
to	O
1	O
TiB	O
DDR4	O
RAM	O
,	O
PowerVM	B-Application
running	O
AIX/IBM	O
i/Linux	O
.	O
</s>
<s>
Power	O
System	O
S922	O
–	O
2U	O
,	O
1	O
–	O
2×	O
POWER9	B-Device
SMT8	O
,	O
4	O
–	O
11	O
cores	O
per	O
processor	O
,	O
up	O
to	O
4	O
TiB	O
DDR4	O
RAM	O
,	O
PowerVM	B-Application
running	O
AIX/IBM	O
i/Linux	O
.	O
</s>
<s>
Power	O
System	O
S924	O
–	O
4U	O
,	O
2×	O
POWER9	B-Device
SMT8	O
,	O
8	O
–	O
12	O
cores	O
per	O
processor	O
,	O
up	O
to	O
4	O
TiB	O
DDR4	O
RAM	O
,	O
PowerVM	B-Application
running	O
AIX/IBM	O
i/Linux	O
.	O
</s>
<s>
Power	O
System	O
H922	O
–	O
2U	O
,	O
1	O
–	O
2×	O
POWER9	B-Device
SMT8	O
,	O
4	O
–	O
10	O
cores	O
per	O
processor	O
,	O
up	O
to	O
4	O
TiB	O
DDR4	O
RAM	O
,	O
PowerVM	B-Application
running	O
SAP	B-Application
HANA	I-Application
(	O
on	O
Linux	B-Application
)	O
with	O
AIX/IBM	O
i	O
on	O
up	O
to	O
25%	O
of	O
the	O
system	O
.	O
</s>
<s>
Power	O
System	O
H924	O
–	O
4U	O
,	O
2×	O
POWER9	B-Device
SMT8	O
,	O
8	O
–	O
12	O
cores	O
per	O
processor	O
,	O
up	O
to	O
4	O
TiB	O
DDR4	O
RAM	O
,	O
PowerVM	B-Application
running	O
SAP	B-Application
HANA	I-Application
(	O
on	O
Linux	B-Application
)	O
with	O
AIX/IBM	O
i	O
on	O
up	O
to	O
25%	O
of	O
the	O
system	O
.	O
</s>
<s>
Hardware	O
Management	O
Console	O
7063-CR2	O
–	O
1U	O
,	O
1×	O
POWER9	B-Device
SMT8	O
,	O
6	O
cores	O
,	O
64-128	O
GB	O
DDR4	O
RAM	O
.	O
</s>
<s>
Summit	B-Device
and	O
Sierra	B-Device
The	O
United	O
States	O
Department	O
of	O
Energy	O
together	O
with	O
Oak	O
Ridge	O
National	O
Laboratory	O
and	O
Lawrence	O
Livermore	O
National	O
Laboratory	O
contracted	O
IBM	O
and	O
Nvidia	O
to	O
build	O
two	O
supercomputers	O
,	O
the	O
Summit	B-Device
and	O
the	O
Sierra	B-Device
,	O
are	O
based	O
on	O
POWER9	B-Device
processors	O
coupled	O
with	O
Nvidia	O
's	O
Volta	B-General_Concept
GPUs	B-Architecture
.	O
</s>
<s>
Sierra	B-Device
is	O
based	O
on	O
IBM	O
's	O
Power	O
Systems	O
AC922	O
compute	O
node	O
.	O
</s>
<s>
The	O
first	O
racks	B-Application
of	O
Summit	B-Device
were	O
delivered	O
to	O
Oak	O
Ridge	O
National	O
Laboratory	O
on	O
31	O
July	O
2017	O
.	O
</s>
<s>
MareNostrum	B-Device
4	O
–	O
One	O
of	O
the	O
three	O
clusters	O
in	O
the	O
emerging	O
technologies	O
block	O
of	O
the	O
fourth	O
MareNostrum	B-Device
supercomputer	I-Device
is	O
a	O
POWER9	B-Device
cluster	O
with	O
Nvidia	B-General_Concept
Volta	I-General_Concept
GPUs	B-Architecture
.	O
</s>
<s>
The	O
emerging	O
technologies	O
block	O
of	O
the	O
MareNostrum	B-Device
4	O
exists	O
to	O
test	O
if	O
new	O
developments	O
might	O
be	O
"	O
suitable	O
for	O
future	O
versions	O
of	O
MareNostrum	B-Device
"	O
.	O
</s>
<s>
As	O
with	O
its	O
predecessor	O
,	O
POWER9	B-Device
is	O
supported	O
by	O
FreeBSD	B-Operating_System
,	O
IBM	B-Application
AIX	I-Application
,	O
IBM	B-Application
i	I-Application
,	O
Linux	B-Application
(	O
both	O
running	O
with	O
and	O
without	O
PowerVM	B-Application
)	O
,	O
and	O
OpenBSD	B-Operating_System
.	O
</s>
<s>
Implementation	O
of	O
POWER9	B-Device
support	O
in	O
the	O
Linux	B-Operating_System
kernel	I-Operating_System
began	O
with	O
version	O
4.6	O
in	O
March	O
2016	O
.	O
</s>
<s>
Red	O
Hat	O
Enterprise	O
Linux	B-Application
(	O
RHEL	O
)	O
,	O
SUSE	O
Linux	B-Application
Enterprise	O
(	O
SLES	O
)	O
,	O
Debian	O
Linux	B-Application
,	O
and	O
CentOS	O
are	O
supported	O
.	O
</s>
<s>
The	O
GNU	B-Application
Guix	I-Application
package	O
manager	O
also	O
supports	O
POWER9	B-Device
,	O
but	O
currently	O
only	O
with	O
another	O
operating	O
system	O
to	O
host	O
it	O
,	O
i.e.	O
</s>
<s>
no	O
GNU	B-Application
Guix	I-Application
System	I-Application
.	O
</s>
