<s>
POWER8	B-Device
is	O
a	O
family	O
of	O
superscalar	B-General_Concept
multi-core	B-Architecture
microprocessors	B-Architecture
based	O
on	O
the	O
Power	B-Architecture
ISA	I-Architecture
,	O
announced	O
in	O
August	O
2013	O
at	O
the	O
Hot	O
Chips	O
conference	O
.	O
</s>
<s>
The	O
designs	O
are	O
available	O
for	O
licensing	O
under	O
the	O
OpenPOWER	B-Application
Foundation	I-Application
,	O
which	O
is	O
the	O
first	O
time	O
for	O
such	O
availability	O
of	O
IBM	O
's	O
highest-end	O
processors	O
.	O
</s>
<s>
Systems	O
based	O
on	O
POWER8	B-Device
became	O
available	O
from	O
IBM	O
in	O
June	O
2014	O
.	O
</s>
<s>
Systems	O
and	O
POWER8	B-Device
processor	O
designs	O
made	O
by	O
other	O
OpenPOWER	B-Application
members	O
were	O
available	O
in	O
early	O
2015	O
.	O
</s>
<s>
POWER8	B-Device
is	O
designed	O
to	O
be	O
a	O
massively	O
multithreaded	O
chip	O
,	O
with	O
each	O
of	O
its	O
cores	O
capable	O
of	O
handling	O
eight	O
hardware	O
threads	O
simultaneously	O
,	O
for	O
a	O
total	O
of	O
96	O
threads	O
executed	O
simultaneously	O
on	O
a	O
12-core	O
chip	O
.	O
</s>
<s>
For	O
most	O
workloads	O
,	O
the	O
chip	O
is	O
said	O
to	O
perform	O
two	O
to	O
three	O
times	O
as	O
fast	O
as	O
its	O
predecessor	O
,	O
the	O
POWER7	B-Device
.	O
</s>
<s>
POWER8	B-Device
chips	O
comes	O
in	O
6	O
-	O
or	O
12-core	O
variants	O
;	O
each	O
version	O
is	O
fabricated	O
in	O
a	O
22	O
nm	O
silicon	B-Algorithm
on	I-Algorithm
insulator	I-Algorithm
(	O
SOI	O
)	O
process	O
using	O
15	O
metal	O
layers	O
.	O
</s>
<s>
However	O
the	O
6	O
-	O
and	O
12-core	O
variants	O
can	O
have	O
all	O
or	O
just	O
some	O
cores	O
active	O
,	O
so	O
POWER8	B-Device
processors	O
come	O
with	O
4	O
,	O
6	O
,	O
8	O
,	O
10	O
or	O
12	O
cores	O
activated	O
.	O
</s>
<s>
Where	O
previous	O
POWER	O
processors	O
use	O
the	O
GX++	O
bus	O
for	O
external	O
communication	O
,	O
POWER8	B-Device
removes	O
this	O
from	O
the	O
design	O
and	O
replaces	O
it	O
with	O
the	O
CAPI	O
port	O
(	O
Coherent	O
Accelerator	O
Processor	O
Interface	O
)	O
that	O
is	O
layered	O
on	O
top	O
of	O
PCI	O
Express	O
3.0	O
.	O
</s>
<s>
The	O
CAPI	O
port	O
is	O
used	O
to	O
connect	O
auxiliary	O
specialized	O
processors	O
such	O
as	O
GPUs	B-Architecture
,	O
ASICs	O
and	O
FPGAs	B-Architecture
.	O
</s>
<s>
At	O
the	O
2013	O
ACM/IEEE	O
Supercomputing	B-Architecture
Conference	O
,	O
IBM	O
and	O
Nvidia	O
announced	O
an	O
engineering	O
partnership	O
to	O
closely	O
couple	O
POWER8	B-Device
with	O
Nvidia	O
GPUs	B-Architecture
in	O
future	O
HPC	B-Architecture
systems	O
,	O
with	O
the	O
first	O
of	O
them	O
announced	O
as	O
the	O
Power	B-Device
Systems	I-Device
S824L	O
.	O
</s>
<s>
Initial	O
members	O
are	O
Google	B-Application
,	O
AMD	O
,	O
Xilinx	O
,	O
Micron	O
and	O
Mellanox	O
.	O
</s>
<s>
POWER8	B-Device
also	O
contains	O
a	O
so-called	O
on-chip	O
controller	O
(	O
OCC	O
)	O
,	O
which	O
is	O
a	O
power	O
and	O
thermal	O
management	O
microcontroller	O
based	O
on	O
a	O
PowerPC	O
405	O
processor	O
.	O
</s>
<s>
It	O
has	O
two	O
general-purpose	O
offload	O
engines	O
(	O
GPEs	O
)	O
and	O
512KB	O
of	O
embedded	O
static	B-Architecture
RAM	I-Architecture
(	O
SRAM	B-Architecture
)	O
(	O
1	O
KB	O
=	O
1024	O
bytes	O
)	O
,	O
together	O
with	O
the	O
possibility	O
to	O
access	O
the	O
main	O
memory	O
directly	O
,	O
while	O
running	O
an	O
open-source	O
firmware	B-Application
.	O
</s>
<s>
OCC	O
manages	O
POWER8	B-Device
's	O
operating	O
frequency	O
,	O
voltage	O
,	O
memory	O
bandwidth	O
,	O
and	O
thermal	O
control	O
for	O
both	O
the	O
processor	O
and	O
memory	O
;	O
it	O
can	O
regulate	O
voltages	O
through	O
1,764	O
integrated	O
voltage	O
regulators	O
(	O
IVRs	O
)	O
on	O
the	O
fly	O
.	O
</s>
<s>
Also	O
,	O
the	O
OCC	O
can	O
be	O
programmed	O
to	O
overclock	B-Application
the	O
POWER8	B-Device
processor	O
,	O
or	O
to	O
lower	O
its	O
power	O
consumption	O
by	O
reducing	O
the	O
operating	O
frequency	O
(	O
which	O
is	O
similar	O
to	O
the	O
configurable	O
TDP	O
found	O
in	O
some	O
of	O
the	O
Intel	O
and	O
AMD	O
processors	O
)	O
.	O
</s>
<s>
POWER8	B-Device
splits	O
the	O
memory	O
controller	O
functions	O
by	O
moving	O
some	O
of	O
them	O
away	O
from	O
the	O
processor	O
and	O
closer	O
to	O
the	O
memory	O
.	O
</s>
<s>
The	O
scheduling	O
logic	O
,	O
the	O
memory	O
energy	O
management	O
,	O
and	O
the	O
RAS	B-General_Concept
decision	O
point	O
are	O
moved	O
to	O
a	O
so-called	O
Memory	O
Buffer	O
chip	O
(	O
a.k.a.	O
</s>
<s>
It	O
runs	O
at	O
8GB/s	O
in	O
the	O
early	O
Entry	O
models	O
,	O
later	O
increased	O
in	O
the	O
high-end	O
and	O
the	O
HPC	B-Architecture
models	O
to	O
9.6GB/s	O
with	O
a	O
40-ns	O
latency	O
,	O
for	O
a	O
sustained	O
bandwidth	O
of	O
24GB/s	O
and	O
28.8GB/s	O
per	O
channel	O
respectively	O
.	O
</s>
<s>
The	O
POWER8	B-Device
core	O
has	O
64KB	O
L1	O
data	O
cache	O
contained	O
in	O
the	O
load-store	B-Architecture
unit	I-Architecture
and	O
32KB	O
L1	O
instruction	O
cache	O
contained	O
in	O
the	O
instruction	O
fetch	O
unit	O
,	O
along	O
with	O
a	O
tightly	O
integrated	O
512	O
KB	O
L2	O
cache	O
.	O
</s>
<s>
Each	O
POWER8	B-Device
core	O
consist	O
of	O
primarily	O
the	O
following	O
six	O
execution	B-General_Concept
units	I-General_Concept
:	O
</s>
<s>
Two	O
fully	O
symmetric	O
vector	O
pipelines	O
with	O
support	O
for	O
VMX	O
and	O
VSX	O
AltiVec	B-General_Concept
instructions	O
.	O
</s>
<s>
POWER8	B-Device
also	O
added	O
support	O
for	O
hardware	B-Operating_System
transactional	I-Operating_System
memory	I-Operating_System
.	O
</s>
<s>
IBM	O
estimates	O
that	O
each	O
core	O
is	O
1.6	O
times	O
as	O
fast	O
as	O
the	O
POWER7	B-Device
in	O
single-threaded	O
operations	O
.	O
</s>
<s>
A	O
POWER8	B-Device
processor	O
is	O
a	O
6	O
-	O
or	O
12-chiplet	O
design	O
with	O
variants	O
of	O
either	O
4	O
,	O
6	O
,	O
8	O
,	O
10	O
or	O
12	O
activated	O
chiplets	O
,	O
in	O
which	O
one	O
chiplet	O
consists	O
of	O
one	O
processing	O
core	O
,	O
512KB	O
of	O
SRAM	B-Architecture
L2	O
cache	O
on	O
a	O
64-byte	O
wide	O
bus	O
(	O
which	O
is	O
twice	O
as	O
wide	O
as	O
on	O
its	O
predecessor	O
)	O
,	O
and	O
8MB	O
of	O
L3	O
eDRAM	O
cache	O
per	O
chiplet	O
shareable	O
among	O
all	O
chiplets	O
.	O
</s>
<s>
The	O
six-core	O
chips	O
are	O
mounted	O
in	O
pairs	O
on	O
dual-chip	O
modules	O
(	O
DCM	O
)	O
in	O
IBM	O
's	O
scale	B-Device
out	I-Device
servers	I-Device
.	O
</s>
<s>
IBM	O
's	O
single-chip	O
POWER8	B-Device
module	O
is	O
called	O
Turismo	O
and	O
the	O
dual-chip	O
variant	O
is	O
called	O
Murano	O
.	O
</s>
<s>
This	O
is	O
a	O
revised	O
version	O
of	O
the	O
original	O
12-core	O
POWER8	B-Device
from	O
IBM	O
,	O
and	O
used	O
to	O
be	O
called	O
POWER8+	O
.	O
</s>
<s>
IBM	O
removed	O
the	O
A	O
Bus	O
and	O
PCI	O
interfaces	O
for	O
SMP	O
connections	O
to	O
other	O
POWER8	B-Device
sockets	O
and	O
replaced	O
them	O
with	O
NVLink	O
interfaces	O
.	O
</s>
<s>
Besides	O
that	O
and	O
a	O
slight	O
size	O
increase	O
to	O
659mm2	O
,	O
the	O
differences	O
seem	O
minimal	O
compared	O
to	O
previous	O
POWER8	B-Device
processors	O
.	O
</s>
<s>
On	O
19	O
January	O
2014	O
,	O
the	O
Suzhou	O
PowerCore	O
Technology	O
Company	O
announced	O
that	O
they	O
will	O
join	O
the	O
OpenPOWER	B-Application
Foundation	I-Application
and	O
license	O
the	O
POWER8	B-Device
core	O
to	O
design	O
custom-made	O
processors	O
for	O
use	O
in	O
big	B-Application
data	I-Application
and	O
cloud	B-Architecture
computing	I-Architecture
applications	O
.	O
</s>
<s>
PowerCore	O
CP1	O
a	O
POWER8	B-Device
variant	O
with	O
revised	O
security	O
features	O
due	O
to	O
export	O
restrictions	O
between	O
United	O
States	O
and	O
China	O
that	O
will	O
be	O
manufactured	O
in	O
GlobalFoundries	O
(	O
formerly	O
IBM	O
's	O
plant	O
)	O
factory	O
in	O
East	O
Fishkill	O
,	O
New	O
York	O
.	O
</s>
<s>
Scale	B-Device
Out	I-Device
servers	I-Device
,	O
supporting	O
one	O
or	O
two	O
sockets	O
each	O
carrying	O
a	O
dual-chip	O
module	O
with	O
two	O
six-core	O
POWER8	B-Device
processors	O
.	O
</s>
<s>
The	O
"	O
L	O
"	O
versions	O
run	O
only	O
Linux	B-Application
,	O
while	O
the	O
others	O
run	O
AIX	B-Application
,	O
IBM	B-Application
i	I-Application
and	O
Linux	B-Application
.	O
</s>
<s>
The	O
"	O
LC	O
"	O
versions	O
are	O
built	O
by	O
OpenPOWER	B-Application
partners	O
.	O
</s>
<s>
Power	B-Device
Systems	I-Device
S821LC	O
"	O
Stratton	O
"	O
2×	O
POWER8	B-Device
SCM	B-Algorithm
(	O
8	O
or	O
10	O
cores	O
)	O
,	O
1U	O
.	O
</s>
<s>
Power	B-Device
Systems	I-Device
S822LC	O
for	O
Big	B-Application
Data	I-Application
"	O
Briggs	O
"	O
2×	O
POWER8	B-Device
SCM	B-Algorithm
(	O
8	O
or	O
10	O
cores	O
)	O
,	O
2U	O
.	O
</s>
<s>
Enterprise	B-Device
servers	I-Device
,	O
supporting	O
nodes	O
with	O
four	O
sockets	O
,	O
each	O
carrying	O
8-	O
,	O
10	O
-	O
or	O
12-core	O
modules	O
,	O
for	O
a	O
maximum	O
of	O
16	O
sockets	O
,	O
128	O
cores	O
and	O
16TB	O
of	O
RAM	O
.	O
</s>
<s>
These	O
machines	O
can	O
run	O
AIX	B-Application
,	O
IBM	O
i	O
,	O
or	O
Linux	B-Application
.	O
</s>
<s>
High	B-Architecture
performance	I-Architecture
computing	I-Architecture
:	O
</s>
<s>
Power	B-Device
Systems	I-Device
S812LC	O
1×	O
POWER8	B-Device
SCM	B-Algorithm
(	O
8	O
or	O
10	O
cores	O
)	O
,	O
2U	O
.	O
</s>
<s>
Power	B-Device
Systems	I-Device
S822LC	O
"	O
Firestone	O
"	O
2×	O
POWER8	B-Device
SCM	B-Algorithm
(	O
8	O
or	O
10	O
cores	O
)	O
,	O
2U	O
.	O
</s>
<s>
Two	O
Nvidia	O
Tesla	B-General_Concept
K80	I-General_Concept
GPUs	B-Architecture
and	O
up	O
to	O
1TB	O
commodity	O
DDR3	O
RAM	O
.	O
</s>
<s>
Power	B-Device
Systems	I-Device
S822LC	O
for	O
HPC	B-Architecture
"	O
Minsky	O
"	O
2×	O
POWER8+	O
SCM	B-Algorithm
(	O
8	O
or	O
10	O
cores	O
)	O
,	O
2U	O
.	O
</s>
<s>
Up	O
to	O
four	O
NVLinked	O
Nvidia	O
Tesla	O
P100	O
GPUs	B-Architecture
and	O
up	O
to	O
1TB	O
commodity	O
DDR4	O
RAM	O
.	O
</s>
<s>
7063-CR1	O
HMC	O
1×	O
POWER8	B-Device
SCM	B-Algorithm
(	O
6	O
cores	O
)	O
,	O
1U	O
.	O
</s>
<s>
An	O
ATX	B-Language
motherboard	I-Language
with	O
one	O
single-chip	O
POWER8	B-Device
socket	O
called	O
the	O
SP010GM2NR	O
.	O
</s>
<s>
Palmetto	O
GN70-BP010	O
,	O
OpenPower	B-Application
reference	O
system	O
.	O
</s>
<s>
2U	O
server	O
,	O
with	O
one	O
four-core	O
POWER8	B-Device
SCM	B-Algorithm
,	O
four	O
RAM	O
sockets	O
,	O
based	O
on	O
a	O
Tyan	O
's	O
motherboard	O
.	O
</s>
<s>
Google	B-Application
has	O
shown	O
a	O
motherboard	O
with	O
two	O
sockets	O
,	O
intended	O
for	O
internal	O
use	O
only	O
.	O
</s>
<s>
Inspur	O
has	O
made	O
a	O
deal	O
with	O
IBM	O
to	O
develop	O
server	O
hardware	O
based	O
on	O
POWER8	B-Device
and	O
related	O
technologies	O
.	O
</s>
<s>
4U	O
server	O
,	O
two	O
POWER8	B-Device
sockets	O
.	O
</s>
<s>
RM4950	O
4U	O
,	O
4-core	O
POWER8	B-Device
SCM	B-Algorithm
with	O
four	O
Nvidia	O
Tesla	O
K40	O
accelerators	O
.	O
</s>
<s>
RedPOWER	O
C210	O
and	O
C220	O
2U	O
and	O
4U	O
servers	O
with	O
two	O
POWER8	B-Device
sockets	O
and	O
64	O
sockets	O
for	O
RAM	O
modules	O
.	O
</s>
<s>
Based	O
on	O
the	O
Open	B-Operating_System
Compute	I-Operating_System
Project	I-Operating_System
platform	O
for	O
use	O
in	O
their	O
OnMetal	O
service	O
.	O
</s>
