<s>
POWER7	B-Device
is	O
a	O
family	O
of	O
superscalar	B-General_Concept
multi-core	B-Architecture
microprocessors	B-Architecture
based	O
on	O
the	O
Power	B-Architecture
ISA	I-Architecture
2.06	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
released	O
in	O
2010	O
that	O
succeeded	O
the	O
POWER6	B-Device
and	O
POWER6+	O
.	O
</s>
<s>
POWER7	B-Device
was	O
developed	O
by	O
IBM	O
at	O
several	O
sites	O
including	O
IBM	O
's	O
Rochester	O
,	O
MN	O
;	O
Austin	O
,	O
TX	O
;	O
Essex	O
Junction	O
,	O
VT	O
;	O
T	O
.	O
J	O
.	O
Watson	B-Application
Research	O
Center	O
,	O
NY	O
;	O
Bromont	O
,	O
QC	O
and	O
IBM	O
Deutschland	O
Research	O
&	O
Development	O
GmbH	O
,	O
Böblingen	O
,	O
Germany	O
laboratories	O
.	O
</s>
<s>
IBM	O
announced	O
servers	O
based	O
on	O
POWER7	B-Device
on	O
8	O
February	O
2010	O
.	O
</s>
<s>
IBM	O
won	O
a	O
$244	O
million	O
DARPA	O
contract	O
in	O
November	O
2006	O
to	O
develop	O
a	O
petascale	B-General_Concept
supercomputer	B-Architecture
architecture	O
before	O
the	O
end	O
of	O
2010	O
in	O
the	O
HPCS	O
project	O
.	O
</s>
<s>
IBM	O
's	O
proposal	O
,	O
PERCS	B-Operating_System
(	O
Productive	O
,	O
Easy-to-use	O
,	O
Reliable	O
Computer	O
System	O
)	O
,	O
which	O
won	O
them	O
the	O
contract	O
,	O
is	O
based	O
on	O
the	O
POWER7	B-Device
processor	O
,	O
AIX	B-Application
operating	I-Application
system	I-Application
and	O
General	B-Application
Parallel	I-Application
File	I-Application
System	I-Application
.	O
</s>
<s>
One	O
feature	O
that	O
IBM	O
and	O
DARPA	O
collaborated	O
on	O
is	O
modifying	O
the	O
addressing	O
and	O
page	O
table	O
hardware	O
to	O
support	O
global	O
shared	O
memory	O
space	O
for	O
POWER7	B-Device
clusters	O
.	O
</s>
<s>
From	O
a	O
productivity	O
standpoint	O
,	O
this	O
is	O
essential	O
since	O
some	O
scientists	O
are	O
not	O
conversant	O
with	O
MPI	B-Application
or	O
other	O
parallel	O
programming	O
techniques	O
used	O
in	O
clusters	O
.	O
</s>
<s>
The	O
POWER7	B-Device
superscalar	B-General_Concept
multi-core	B-Architecture
architecture	O
was	O
a	O
substantial	O
evolution	O
from	O
the	O
POWER6	B-Device
design	O
,	O
focusing	O
more	O
on	O
power	O
efficiency	O
through	O
multiple	O
cores	O
and	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
.	O
</s>
<s>
The	O
POWER6	B-Device
architecture	O
was	O
built	O
from	O
the	O
ground	O
up	O
to	O
maximize	O
processor	O
frequency	O
at	O
the	O
cost	O
of	O
power	O
efficiency	O
.	O
</s>
<s>
While	O
the	O
POWER6	B-Device
features	O
a	O
dual-core	B-Architecture
processor	I-Architecture
,	O
each	O
capable	O
of	O
two-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
,	O
the	O
IBM	O
POWER	O
7	O
processor	O
has	O
up	O
to	O
eight	O
cores	O
,	O
and	O
four	O
threads	B-Operating_System
per	O
core	O
,	O
for	O
a	O
total	O
capacity	O
of	O
32	O
simultaneous	O
threads	B-Operating_System
.	O
</s>
<s>
IBM	O
stated	O
at	O
ISCA	O
29	O
that	O
peak	O
performance	O
was	O
achieved	O
by	O
high	O
frequency	O
designs	O
with	O
10	O
–	O
20	O
FO4	O
delays	O
per	O
pipeline	B-General_Concept
stage	O
at	O
the	O
cost	O
of	O
power	O
efficiency	O
.	O
</s>
<s>
However	O
,	O
the	O
POWER6	B-Device
binary	B-Algorithm
floating-point	I-Algorithm
unit	O
achieves	O
a	O
"	O
6-cycle	O
,	O
13-FO4	O
pipeline	B-General_Concept
"	O
.	O
</s>
<s>
Therefore	O
,	O
the	O
pipeline	B-General_Concept
for	O
the	O
POWER7	B-Device
CPU	O
has	O
been	O
changed	O
again	O
,	O
just	O
as	O
it	O
was	O
for	O
the	O
POWER5	O
and	O
POWER6	B-Device
designs	O
.	O
</s>
<s>
In	O
some	O
respects	O
,	O
this	O
rework	O
is	O
similar	O
to	O
Intel	O
's	O
turn	O
in	O
2005	O
that	O
left	O
the	O
P4	O
7th-generation	O
x86	O
microarchitecture	B-General_Concept
.	O
</s>
<s>
The	O
POWER7	B-Device
is	O
available	O
with	O
4	O
,	O
6	O
,	O
or	O
8	O
physical	O
cores	O
per	O
microchip	O
,	O
in	O
a	O
1	O
to	O
32-way	O
design	O
,	O
with	O
up	O
to	O
1024	O
SMTs	O
and	O
a	O
slightly	O
different	O
microarchitecture	B-General_Concept
and	O
interfaces	O
for	O
supporting	O
extended/Sub	O
-Specifications	O
in	O
reference	O
to	O
the	O
Power	B-Architecture
ISA	I-Architecture
and/or	O
different	O
system	O
architectures	O
.	O
</s>
<s>
For	O
example	O
,	O
in	O
the	O
Supercomputing	B-Architecture
(	O
HPC	O
)	O
System	O
Power	O
775	O
it	O
is	O
packaged	O
as	O
a	O
32-way	O
quad-chip-module	O
(	O
QCM	O
)	O
with	O
256	O
physical	O
cores	O
and	O
1024	O
SMTs	O
.	O
</s>
<s>
There	O
is	O
also	O
a	O
special	O
TurboCore	O
mode	O
that	O
can	O
turn	O
off	O
half	O
of	O
the	O
cores	O
from	O
an	O
eight-core	O
processor	O
,	O
but	O
those	O
4	O
cores	O
have	O
access	O
to	O
all	O
the	O
memory	O
controllers	O
and	O
L3	O
cache	B-General_Concept
at	O
increased	O
clock	O
speeds	O
.	O
</s>
<s>
The	O
new	O
IBM	O
Power	O
780	O
scalable	O
,	O
high-end	O
servers	O
featuring	O
the	O
new	O
TurboCore	O
workload	O
optimizing	O
mode	O
and	O
delivering	O
up	O
to	O
double	O
performance	O
per	O
core	O
of	O
POWER6	B-Device
based	O
systems	O
.	O
</s>
<s>
Each	O
core	O
is	O
capable	O
of	O
four-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
.	O
</s>
<s>
The	O
POWER7	B-Device
has	O
approximately	O
1.2	O
billion	O
transistors	B-Application
and	O
is	O
567mm2	O
large	O
fabricated	O
on	O
a	O
45nm	B-Algorithm
process	O
.	O
</s>
<s>
A	O
notable	O
difference	O
from	O
POWER6	B-Device
is	O
that	O
the	O
POWER7	B-Device
executes	O
instructions	O
out-of-order	O
instead	O
of	O
in-order	O
.	O
</s>
<s>
Despite	O
the	O
decrease	O
in	O
maximum	O
frequency	O
compared	O
to	O
POWER6	B-Device
(	O
4.25GHz	O
vs	O
5.0GHz	O
)	O
,	O
each	O
core	O
has	O
higher	O
performance	O
than	O
the	O
POWER6	B-Device
,	O
while	O
each	O
processor	O
has	O
up	O
to	O
4	O
times	O
the	O
number	O
of	O
cores	O
.	O
</s>
<s>
POWER7	B-Device
has	O
these	O
specifications	O
:	O
</s>
<s>
4	O
MB	O
L3	O
cache	B-General_Concept
per	O
C1	O
core	O
with	O
maximum	O
up	O
to	O
32MB	O
supported	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
is	O
implemented	O
in	O
eDRAM	O
,	O
which	O
does	O
not	O
require	O
as	O
many	O
transistors	B-Application
per	O
cell	O
as	O
a	O
standard	O
SRAM	B-Architecture
so	O
it	O
allows	O
for	O
a	O
larger	O
cache	B-General_Concept
while	O
using	O
the	O
same	O
area	O
as	O
SRAM	B-Architecture
.	O
</s>
<s>
Each	O
POWER7	B-Device
processor	O
core	O
implements	O
aggressive	O
out-of-order	O
(	O
OoO	O
)	O
instruction	O
execution	O
to	O
drive	O
high	O
efficiency	O
in	O
the	O
use	O
of	O
available	O
execution	O
paths	O
.	O
</s>
<s>
The	O
POWER7	B-Device
processor	O
has	O
an	O
Instruction	O
Sequence	O
Unit	O
that	O
is	O
capable	O
of	O
dispatching	O
up	O
to	O
six	O
instructions	O
per	O
cycle	O
to	O
a	O
set	O
of	O
queues	O
.	O
</s>
<s>
For	O
comparison	O
,	O
Intel	O
's	O
2013	O
Haswell	B-Device
architecture	O
CPUs	O
can	O
do	O
16	O
DP	O
FLOPs	O
or	O
32	O
SP	O
FLOPs	O
per	O
cycle	O
(	O
8/16	O
DP/SP	O
fused	O
multiply-add	O
spread	O
across	O
2×	O
256-bit	O
AVX2	O
FP	O
vector	O
units	O
)	O
.	O
</s>
<s>
At	O
3.4GHz	O
(	O
i7-4770	O
)	O
this	O
translates	O
into	O
108.8	O
SP	O
GFLOPS	O
per	O
core	O
and	O
435.2	O
SP	O
GFLOPS	O
peak	O
performance	O
across	O
the	O
4-core	O
chip	O
,	O
giving	O
roughly	O
similar	O
levels	O
of	O
performance	O
per	O
core	O
,	O
without	O
taking	O
into	O
account	O
the	O
effects	O
or	O
benefits	O
of	O
Intel	O
's	O
Turbo	B-Device
Boost	I-Device
technology	O
.	O
</s>
<s>
This	O
theoretical	O
peak	O
performance	O
comparison	O
holds	O
in	O
practice	O
too	O
,	O
with	O
the	O
POWER7	B-Device
and	O
the	O
i7-4770	O
obtaining	O
similar	O
scores	O
in	O
the	O
SPEC	O
CPU2006	O
floating	B-Algorithm
point	I-Algorithm
benchmarks	O
(	O
single-threaded	O
)	O
:	O
71.5	O
for	O
POWER7	B-Device
versus	O
74.0	O
for	O
i7-4770	O
.	O
</s>
<s>
Notice	O
that	O
the	O
POWER7	B-Device
chip	O
significantly	O
outperformed	O
(	O
2×	O
–	O
5×	O
)	O
the	O
i7	O
in	O
some	O
benchmarks	O
(	O
bwaves	O
,	O
cactusADM	O
,	O
lbm	O
)	O
while	O
also	O
being	O
significantly	O
slower	O
(	O
2x-3x	O
)	O
in	O
most	O
others	O
.	O
</s>
<s>
However	O
,	O
overall	O
,	O
in	O
a	O
very	O
broad	O
sense	O
,	O
one	O
can	O
say	O
that	O
the	O
floating-point	B-Algorithm
performance	O
of	O
the	O
POWER7	B-Device
is	O
similar	O
to	O
that	O
of	O
the	O
Haswelli7	O
.	O
</s>
<s>
IBM	O
introduced	O
the	O
POWER7+	O
processor	O
at	O
the	O
Hot	O
Chips	O
24	O
conference	O
in	O
August	O
2012	O
.	O
</s>
<s>
It	O
is	O
an	O
updated	O
version	O
with	O
higher	O
speeds	O
,	O
more	O
cache	B-General_Concept
and	O
integrated	O
accelerators	O
.	O
</s>
<s>
The	O
first	O
boxes	O
to	O
ship	O
with	O
the	O
POWER7+	O
processors	O
were	O
IBM	O
Power	O
770	O
and	O
780	O
servers	O
.	O
</s>
<s>
The	O
chips	O
have	O
up	O
to	O
80	O
MB	O
of	O
L3	O
cache	B-General_Concept
(	O
10	O
MB/core	O
)	O
,	O
improved	O
clock	O
speeds	O
(	O
up	O
to	O
4.4GHz	O
)	O
and	O
20	O
LPARs	B-Device
per	O
core	O
.	O
</s>
<s>
,	O
the	O
range	O
of	O
POWER7-based	O
systems	O
including	O
IBM	B-Device
Power	I-Device
Systems	I-Device
"	O
Express	O
"	O
models	O
(	O
710	O
,	O
720	O
,	O
730	O
,	O
740	O
and	O
750	O
)	O
,	O
Enterprise	O
models	O
(	O
770	O
,	O
780	O
and	O
795	O
)	O
and	O
High	B-Architecture
Performance	I-Architecture
computing	I-Architecture
models	O
(	O
755	O
and	O
775	O
)	O
.	O
</s>
<s>
IBM	O
also	O
offers	O
5	O
POWER7	B-Device
based	O
BladeCenters	B-General_Concept
.	O
</s>
<s>
The	O
following	O
are	O
supercomputer	B-Architecture
projects	O
that	O
use	O
the	O
POWER7	B-Device
processor	O
:	O
</s>
