<s>
The	O
POWER6	B-Device
is	O
a	O
microprocessor	B-Architecture
developed	O
by	O
IBM	O
that	O
implemented	O
the	O
Power	B-Architecture
ISA	I-Architecture
v.2.03	O
.	O
</s>
<s>
When	O
it	O
became	O
available	O
in	O
systems	O
in	O
2007	O
,	O
it	O
succeeded	O
the	O
POWER5+	O
as	O
IBM	O
's	O
flagship	O
Power	O
microprocessor	B-Architecture
.	O
</s>
<s>
It	O
is	O
claimed	O
to	O
be	O
part	O
of	O
the	O
eCLipz	B-Device
project	I-Device
,	O
said	O
to	O
have	O
a	O
goal	O
of	O
converging	O
IBM	O
's	O
server	O
hardware	O
where	O
practical	O
(	O
hence	O
"	O
ipz	O
"	O
in	O
the	O
acronym	O
:	O
iSeries	B-Device
,	O
pSeries	O
,	O
and	O
zSeries	O
)	O
.	O
</s>
<s>
POWER6	B-Device
was	O
described	O
at	O
the	O
International	O
Solid-State	O
Circuits	O
Conference	O
(	O
ISSCC	O
)	O
in	O
February	O
2006	O
,	O
and	O
additional	O
details	O
were	O
added	O
at	O
the	O
Microprocessor	B-Architecture
Forum	O
in	O
October	O
2006	O
and	O
at	O
the	O
next	O
ISSCC	O
in	O
February	O
2007	O
.	O
</s>
<s>
POWER6	B-Device
reached	O
first	O
silicon	O
in	O
the	O
middle	O
of	O
2005	O
,	O
and	O
was	O
bumped	O
to	O
5.0GHz	O
in	O
May	O
2008	O
with	O
the	O
introduction	O
of	O
the	O
P595	O
.	O
</s>
<s>
The	O
POWER6	B-Device
is	O
a	O
dual-core	B-Architecture
processor	I-Architecture
.	O
</s>
<s>
Each	O
core	O
is	O
capable	O
of	O
two-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
.	O
</s>
<s>
The	O
POWER6	B-Device
has	O
approximately	O
790	O
million	O
transistors	O
and	O
is	O
341mm2	O
large	O
fabricated	O
on	O
a	O
65	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
.	O
</s>
<s>
A	O
notable	O
difference	O
from	O
POWER5	B-Device
is	O
that	O
the	O
POWER6	B-Device
executes	O
instructions	O
in-order	O
instead	O
of	O
out-of-order	B-General_Concept
.	O
</s>
<s>
This	O
change	O
often	O
requires	O
software	O
to	O
be	O
recompiled	O
for	O
optimal	O
performance	O
,	O
but	O
the	O
POWER6	B-Device
still	O
achieves	O
significant	O
performance	O
improvements	O
over	O
the	O
POWER5+	O
even	O
with	O
unmodified	O
software	O
,	O
according	O
to	O
the	O
lead	O
engineer	O
on	O
the	O
POWER6	B-Device
project	O
.	O
</s>
<s>
POWER6	B-Device
also	O
takes	O
advantage	O
of	O
ViVA-2	B-Device
,	O
Virtual	B-Device
Vector	I-Device
Architecture	I-Device
,	O
which	O
enables	O
the	O
combination	O
of	O
several	O
POWER6	B-Device
nodes	O
to	O
act	O
as	O
a	O
single	O
vector	B-Operating_System
processor	I-Operating_System
.	O
</s>
<s>
Each	O
core	O
has	O
two	O
integer	B-General_Concept
units	I-General_Concept
,	O
two	O
binary	B-Algorithm
floating-point	I-Algorithm
units	O
,	O
an	O
AltiVec	B-General_Concept
unit	O
,	O
and	O
a	O
novel	O
decimal	O
floating-point	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
The	O
binary	B-Algorithm
floating-point	I-Algorithm
unit	O
incorporates	O
"	O
many	O
microarchitectures	O
,	O
logic	O
,	O
circuit	O
,	O
latch	O
and	O
integration	O
techniques	O
to	O
achieve	O
 [ a ] 	O
6-cycle	O
,	O
13-FO4	O
pipeline	O
"	O
,	O
according	O
to	O
a	O
company	O
paper	O
.	O
</s>
<s>
Unlike	O
the	O
servers	O
from	O
IBM	O
's	O
competitors	O
,	O
the	O
POWER6	B-Device
has	O
hardware	O
support	O
for	O
IEEE	O
754	O
decimal	O
arithmetic	O
and	O
includes	O
the	O
first	O
decimal	O
floating-point	B-General_Concept
unit	I-General_Concept
integrated	O
in	O
silicon	O
.	O
</s>
<s>
More	O
than	O
50	O
new	O
floating	B-Algorithm
point	I-Algorithm
instructions	O
handle	O
the	O
decimal	O
math	O
and	O
conversions	O
between	O
binary	O
and	O
decimal	O
.	O
</s>
<s>
This	O
feature	O
was	O
also	O
added	O
to	O
the	O
z10	B-Device
microprocessor	B-Architecture
featured	O
in	O
the	O
System	B-Device
z10	I-Device
.	O
</s>
<s>
POWER6	B-Device
can	O
connect	O
to	O
up	O
to	O
31	O
other	O
processors	O
using	O
two	O
inter	O
node	O
links	O
(	O
50	O
GB/s	O
)	O
,	O
and	O
supports	O
up	O
to	O
10	O
logical	O
partitions	O
per	O
core	O
(	O
up	O
to	O
a	O
limit	O
of	O
254	O
per	O
system	O
)	O
.	O
</s>
<s>
The	O
POWER6	B-Device
design	O
uses	O
dual	O
power	O
supplies	O
,	O
a	O
logic	O
supply	O
in	O
the	O
0.8-to-1.2	O
Volt	O
range	O
and	O
an	O
SRAM	O
power	O
supply	O
at	O
about	O
150-mV	O
higher	O
.	O
</s>
<s>
The	O
thermal	O
characteristics	O
of	O
POWER6	B-Device
are	O
similar	O
to	O
that	O
of	O
the	O
POWER5	B-Device
.	O
</s>
<s>
Dr	O
Frank	O
Soltis	O
,	O
an	O
IBM	O
chief	O
scientist	O
,	O
said	O
IBM	O
had	O
solved	O
power	O
leakage	O
problems	O
associated	O
with	O
high	O
frequency	O
by	O
using	O
a	O
combination	O
of	O
90	O
nm	O
and	O
65nm	B-Algorithm
parts	O
in	O
the	O
POWER6	B-Device
design	O
.	O
</s>
<s>
The	O
slightly	O
enhanced	O
POWER6+	O
was	O
introduced	O
in	O
April	O
2009	O
,	O
but	O
had	O
been	O
shipping	O
in	O
Power	B-Device
560	I-Device
and	I-Device
570	I-Device
systems	O
since	O
October	O
2008	O
.	O
</s>
<s>
It	O
added	O
more	O
memory	O
keys	O
for	O
secure	O
memory	O
partition	O
,	O
a	O
feature	O
taken	O
from	O
IBM	O
's	O
mainframe	B-Device
processors	I-Device
.	O
</s>
<s>
,	O
the	O
range	O
of	O
POWER6	B-Device
systems	O
includes	O
"	O
Express	O
"	O
models	O
(	O
the	O
520	O
,	O
550	O
and	O
560	O
)	O
and	O
Enterprise	O
models	O
(	O
the	O
570	O
and	O
595	O
)	O
.	O
</s>
<s>
IBM	O
also	O
offers	O
four	O
POWER6	B-Device
based	O
blade	B-Architecture
servers	I-Architecture
.	O
</s>
<s>
All	O
blades	O
support	O
AIX	B-Application
,	O
IBM	B-Application
i	I-Application
,	O
and	O
Linux	B-Application
.	O
</s>
<s>
The	O
BladeCenter	B-General_Concept
S	O
and	O
H	O
chassis	O
is	O
supported	O
for	O
blades	O
running	O
AIX	B-Application
,	O
i	O
,	O
and	O
Linux	B-Application
.	O
</s>
<s>
The	O
BladeCenter	B-General_Concept
E	O
,	O
HT	O
,	O
and	O
T	O
chassis	O
support	O
blades	O
running	O
AIX	B-Application
and	O
Linux	B-Application
but	O
not	O
i	O
.	O
</s>
<s>
The	O
575	O
is	O
composed	O
of	O
2U	O
"	O
nodes	O
"	O
each	O
with	O
32	O
POWER6	B-Device
cores	O
at	O
4.7GHz	O
with	O
up	O
to	O
256	O
GB	O
of	O
RAM	O
.	O
</s>
