<s>
The	O
POWER5	B-Device
is	O
a	O
microprocessor	B-Architecture
developed	O
and	O
fabricated	O
by	O
IBM	O
.	O
</s>
<s>
It	O
is	O
an	O
improved	O
version	O
of	O
the	O
POWER4	B-Device
.	O
</s>
<s>
The	O
principal	O
improvements	O
are	O
support	O
for	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
and	O
an	O
on-die	O
memory	B-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
The	O
POWER5	B-Device
is	O
a	O
dual-core	B-Architecture
microprocessor	B-Architecture
,	O
with	O
each	O
core	O
supporting	O
one	O
physical	O
thread	B-Operating_System
and	O
two	O
logical	O
threads	B-Operating_System
,	O
for	O
a	O
total	O
of	O
two	O
physical	O
threads	B-Operating_System
and	O
four	O
logical	O
threads	B-Operating_System
.	O
</s>
<s>
Technical	O
details	O
of	O
the	O
microprocessor	B-Architecture
were	O
first	O
presented	O
at	O
the	O
2003	O
Hot	O
Chips	O
conference	O
.	O
</s>
<s>
A	O
more	O
complete	O
description	O
was	O
given	O
at	O
Microprocessor	B-Architecture
Forum	O
2003	O
on	O
14	O
October	O
2003	O
.	O
</s>
<s>
The	O
POWER5	B-Device
was	O
not	O
sold	O
openly	O
and	O
was	O
used	O
exclusively	O
by	O
IBM	O
and	O
their	O
partners	O
.	O
</s>
<s>
Systems	O
using	O
the	O
microprocessor	B-Architecture
were	O
introduced	O
in	O
2004	O
.	O
</s>
<s>
The	O
POWER5	B-Device
competed	O
in	O
the	O
high-end	O
enterprise	O
server	O
market	O
,	O
mostly	O
against	O
the	O
Intel	O
Itanium	O
2	O
and	O
to	O
a	O
lesser	O
extent	O
,	O
the	O
Sun	O
Microsystems	O
UltraSPARC	B-General_Concept
IV	I-General_Concept
and	O
the	O
Fujitsu	O
SPARC64	B-Device
V	I-Device
.	O
It	O
was	O
superseded	O
in	O
2005	O
by	O
an	O
improved	O
iteration	O
,	O
the	O
POWER5+	O
.	O
</s>
<s>
The	O
POWER5	B-Device
is	O
a	O
further	O
development	O
of	O
the	O
POWER4	B-Device
.	O
</s>
<s>
The	O
addition	O
of	O
two-way	O
multithreading	B-General_Concept
required	O
the	O
duplication	O
of	O
the	O
return	O
stack	O
,	O
program	B-General_Concept
counter	I-General_Concept
,	O
instruction	O
buffer	O
,	O
group	O
completion	O
unit	O
and	O
store	O
queue	O
so	O
that	O
each	O
thread	B-Operating_System
may	O
have	O
its	O
own	O
.	O
</s>
<s>
Most	O
resources	O
,	O
such	O
as	O
the	O
register	O
files	O
and	O
execution	O
units	O
,	O
are	O
shared	O
,	O
although	O
each	O
thread	B-Operating_System
sees	O
its	O
own	O
set	O
of	O
registers	O
.	O
</s>
<s>
The	O
POWER5	B-Device
implements	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
,	O
where	O
two	O
threads	B-Operating_System
are	O
executed	O
simultaneously	O
.	O
</s>
<s>
The	O
POWER5	B-Device
can	O
disable	O
SMT	O
to	O
optimize	O
for	O
the	O
current	O
workload	O
.	O
</s>
<s>
As	O
many	O
resources	O
such	O
as	O
the	O
register	O
files	O
are	O
shared	O
by	O
two	O
threads	B-Operating_System
,	O
they	O
are	O
increased	O
in	O
capacity	O
in	O
many	O
cases	O
to	O
compensate	O
for	O
the	O
loss	O
of	O
performance	O
.	O
</s>
<s>
The	O
number	O
of	O
integer	O
and	O
floating-point	O
registers	O
is	O
increased	O
to	O
120	O
each	O
,	O
from	O
80	O
integer	O
and	O
72	O
floating-point	O
registers	O
in	O
the	O
POWER4	B-Device
.	O
</s>
<s>
Like	O
the	O
POWER4	B-Device
,	O
the	O
cache	O
is	O
shared	O
by	O
the	O
two	O
cores	O
.	O
</s>
<s>
The	O
on-die	O
memory	B-General_Concept
controller	I-General_Concept
supports	O
up	O
to	O
64GB	O
of	O
DDR	O
and	O
DDR2	O
memory	O
.	O
</s>
<s>
It	O
uses	O
high-frequency	O
serial	O
buses	O
to	O
communicate	O
with	O
external	O
buffers	O
that	O
interface	O
the	O
dual	B-General_Concept
inline	I-General_Concept
memory	I-General_Concept
modules	I-General_Concept
(	O
DIMMs	B-General_Concept
)	O
to	O
the	O
microprocessor	B-Architecture
.	O
</s>
<s>
The	O
POWER5	B-Device
contains	O
276	O
million	O
transistors	O
and	O
has	O
an	O
area	O
of	O
389mm2	O
.	O
</s>
<s>
It	O
is	O
fabricated	O
by	O
IBM	O
in	O
a	O
0.13μm	O
silicon	B-Algorithm
on	I-Algorithm
insulator	I-Algorithm
(	O
SOI	O
)	O
complementary	O
metal	O
–	O
oxide	O
–	O
semiconductor	O
(	O
CMOS	O
)	O
process	O
with	O
eight	O
layers	O
of	O
copper	O
interconnect	O
.	O
</s>
<s>
The	O
POWER5	B-Device
die	O
is	O
packaged	O
in	O
either	O
a	O
dual	O
chip	O
module	O
(	O
DCM	O
)	O
or	O
a	O
multi-chip	B-Algorithm
module	I-Algorithm
(	O
MCM	B-Algorithm
)	O
.	O
</s>
<s>
The	O
DCM	O
contains	O
one	O
POWER5	B-Device
die	O
and	O
its	O
associated	O
L3	O
cache	O
die	O
.	O
</s>
<s>
The	O
MCM	B-Algorithm
contains	O
four	O
POWER5	B-Device
dies	O
and	O
four	O
L3	O
cache	O
dies	O
,	O
one	O
for	O
each	O
POWER5	B-Device
die	O
,	O
and	O
measures	O
95mm	O
by	O
95mm	O
.	O
</s>
<s>
Several	O
POWER5	B-Device
processors	O
in	O
high-end	O
systems	O
can	O
be	O
coupled	O
together	O
to	O
act	O
as	O
a	O
single	O
vector	B-Operating_System
processor	I-Operating_System
by	O
a	O
technology	O
called	O
ViVA	B-Device
(	O
Virtual	B-Device
Vector	I-Device
Architecture	I-Device
)	O
.	O
</s>
<s>
The	O
POWER5+	O
is	O
an	O
improved	O
iteration	O
of	O
the	O
POWER5	B-Device
introduced	O
on	O
4	O
October	O
2005	O
.	O
</s>
<s>
The	O
POWER5+	O
chip	O
uses	O
a	O
90nm	O
fabrication	O
process	O
.	O
</s>
<s>
The	O
POWER5+	O
was	O
packaged	O
in	O
the	O
same	O
packages	O
as	O
previous	O
POWER5	B-Device
microprocessors	B-Architecture
,	O
but	O
was	O
also	O
available	O
in	O
a	O
quad-chip	O
module	O
(	O
QCM	O
)	O
containing	O
two	O
POWER5+	O
dies	O
and	O
two	O
L3	O
cache	O
dies	O
,	O
one	O
for	O
each	O
POWER5+	O
die	O
.	O
</s>
<s>
IBM	O
uses	O
the	O
DCM	O
and	O
MCM	B-Algorithm
POWER5	B-Device
microprocessors	B-Architecture
in	O
its	O
System	O
p	O
and	O
System	O
i	O
server	O
families	O
,	O
in	O
its	O
DS8000	B-Device
storage	O
server	O
,	O
and	O
as	O
embedded	B-Architecture
microprocessors	I-Architecture
in	O
its	O
high-end	O
Infoprint	O
printers	O
.	O
</s>
<s>
DCM	O
POWER5	B-Device
microprocessors	B-Architecture
are	O
used	O
by	O
IBM	O
in	O
its	O
high-end	O
IntelliStation	B-Device
POWER	O
285	O
workstation	O
.	O
</s>
<s>
Third-party	O
users	O
of	O
POWER5	B-Device
microprocessors	B-Architecture
are	O
Groupe	O
Bull	O
,	O
in	O
its	O
Escala	O
servers	O
,	O
and	O
Hitachi	O
,	O
in	O
its	O
SR11000	O
computers	O
with	O
up	O
to	O
128	O
POWER5+	O
microprocessors	B-Architecture
,	O
which	O
have	O
several	O
installations	O
featured	O
in	O
the	O
2007	O
TOP500	B-Operating_System
list	B-Operating_System
of	I-Operating_System
supercomputers	I-Operating_System
.	O
</s>
<s>
IBM	O
uses	O
the	O
POWER5+	O
QCM	O
in	O
its	O
Systemp5	O
510Q	O
,	O
520Q	O
,	O
550Q	O
and	O
560Q	O
servers	O
.	O
</s>
