<s>
The	O
POWER4	B-Device
is	O
a	O
microprocessor	B-Architecture
developed	O
by	O
International	O
Business	O
Machines	O
(	O
IBM	O
)	O
that	O
implemented	O
the	O
64-bit	B-Device
PowerPC	B-Architecture
and	O
PowerPC	B-Architecture
AS	O
instruction	B-General_Concept
set	I-General_Concept
architectures	I-General_Concept
.	O
</s>
<s>
Released	O
in	O
2001	O
,	O
the	O
POWER4	B-Device
succeeded	O
the	O
POWER3	B-General_Concept
and	O
RS64	B-Device
microprocessors	B-Architecture
,	O
enabling	O
RS/6000	B-Device
and	O
eServer	B-Device
iSeries	I-Device
models	I-Device
of	I-Device
AS/400	I-Device
computer	O
servers	O
to	O
run	O
on	O
the	O
same	O
processor	O
,	O
as	O
a	O
step	O
toward	O
converging	O
the	O
two	O
lines	O
.	O
</s>
<s>
The	O
POWER4	B-Device
was	O
a	O
multicore	B-Architecture
microprocessor	B-Architecture
,	O
with	O
two	O
cores	O
on	O
a	O
single	O
die	O
,	O
the	O
first	O
non-embedded	O
microprocessor	B-Architecture
to	O
do	O
so	O
.	O
</s>
<s>
POWER4	B-Device
Chip	O
was	O
first	O
commercially	O
available	O
multiprocessor	O
chip	O
.	O
</s>
<s>
The	O
original	O
POWER4	B-Device
had	O
a	O
clock	O
speed	O
of	O
1.1	O
and	O
1.3GHz	O
,	O
while	O
an	O
enhanced	O
version	O
,	O
the	O
POWER4+	B-Device
,	O
reached	O
a	O
clock	O
speed	O
of	O
1.9GHz	O
.	O
</s>
<s>
The	O
PowerPC	B-General_Concept
970	I-General_Concept
is	O
a	O
derivative	O
of	O
the	O
POWER4	B-Device
.	O
</s>
<s>
The	O
POWER4	B-Device
has	O
a	O
unified	O
L2	O
cache	O
,	O
divided	O
into	O
three	O
equal	O
parts	O
.	O
</s>
<s>
The	O
Fabric	O
Controller	O
is	O
the	O
master	O
controller	O
for	O
the	O
network	O
of	O
buses	O
,	O
controlling	O
communications	O
for	O
both	O
L1/L2	O
controllers	O
,	O
communications	O
between	O
POWER4	B-Device
chips	O
{	O
4-way	O
,	O
8-way	O
,	O
16-way	O
,	O
32-way	O
}	O
and	O
POWER4	B-Device
MCM	O
's	O
.	O
</s>
<s>
Power-on	B-Application
reset	I-Application
(	O
POR	O
)	O
is	O
supported	O
.	O
</s>
<s>
The	O
POWER4	B-Device
implements	O
a	O
superscalar	B-General_Concept
microarchitecture	B-General_Concept
through	O
high-frequency	O
speculative	B-General_Concept
out-of-order	B-General_Concept
execution	I-General_Concept
using	O
eight	O
independent	O
execution	O
units	O
.	O
</s>
<s>
The	O
POWER4	B-Device
also	O
came	O
in	O
a	O
configuration	O
using	O
a	O
multi-chip	B-Algorithm
module	I-Algorithm
(	O
MCM	O
)	O
containing	O
four	O
POWER4	B-Device
dies	O
in	O
a	O
single	O
package	O
,	O
with	O
up	O
to	O
128	O
MB	O
of	O
shared	O
L3	O
ECC	O
cache	O
per	O
MCM	O
.	O
</s>
<s>
The	O
POWER4+	B-Device
,	O
released	O
in	O
2003	O
,	O
was	O
an	O
improved	O
version	O
of	O
the	O
POWER4	B-Device
that	O
ran	O
at	O
up	O
to	O
1.9GHz	O
.	O
</s>
