<s>
The	O
POWER2	B-General_Concept
,	O
originally	O
named	O
RIOS2	O
,	O
is	O
a	O
processor	B-General_Concept
designed	O
by	O
IBM	O
that	O
implemented	O
the	O
POWER	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
The	O
POWER2	B-General_Concept
was	O
the	O
successor	O
of	O
the	O
POWER1	B-General_Concept
,	O
debuting	O
in	O
September	O
1993	O
within	O
IBM	O
's	O
RS/6000	B-Device
systems	O
.	O
</s>
<s>
When	O
introduced	O
,	O
the	O
POWER2	B-General_Concept
was	O
the	O
fastest	O
microprocessor	O
,	O
surpassing	O
the	O
Alpha	B-General_Concept
21064	I-General_Concept
.	O
</s>
<s>
When	O
the	O
Alpha	B-General_Concept
21064A	I-General_Concept
was	O
introduced	O
in	O
1993	O
,	O
the	O
POWER2	B-General_Concept
lost	O
the	O
lead	O
and	O
became	O
second	O
.	O
</s>
<s>
IBM	O
claimed	O
that	O
the	O
performance	O
for	O
a	O
62.5MHz	O
POWER2	B-General_Concept
was	O
73.3	O
SPECint92	O
and	O
134.6	O
SPECfp92	O
.	O
</s>
<s>
The	O
open	O
source	O
GCC	B-Application
compiler	I-Application
removed	O
support	O
for	O
POWER1	B-General_Concept
(	O
RIOS	O
)	O
and	O
POWER2	B-General_Concept
(	O
RIOS2	O
)	O
in	O
the	O
4.5	O
release	O
.	O
</s>
<s>
Improvements	O
over	O
the	O
POWER1	B-General_Concept
included	O
enhancements	O
to	O
the	O
POWER	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
consisting	O
of	O
new	O
user	O
and	O
system	O
instructions	O
and	O
other	O
system-related	O
features	O
)	O
,	O
higher	O
clock	O
rates	O
(	O
55	O
to	O
71.5MHz	O
)	O
,	O
an	O
extra	O
fixed	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
and	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
,	O
a	O
larger	O
32KB	O
instruction	O
cache	O
,	O
and	O
a	O
larger	O
128	O
or	O
256KB	O
data	O
cache	O
.	O
</s>
<s>
The	O
POWER2	B-General_Concept
was	O
a	O
multi-chip	O
design	O
consisting	O
of	O
six	O
or	O
eight	O
semi-custom	O
integrated	O
circuits	O
,	O
depending	O
on	O
the	O
amount	O
of	O
data	O
cache	O
(	O
the	O
256KB	O
configuration	O
required	O
eight	O
chips	O
)	O
.	O
</s>
<s>
The	O
partitioning	O
of	O
the	O
design	O
was	O
identical	O
to	O
that	O
of	O
the	O
POWER1	B-General_Concept
:	O
an	O
instruction	O
cache	O
unit	O
chip	O
,	O
a	O
fixed-point	O
unit	O
chip	O
,	O
a	O
floating-point	B-General_Concept
unit	I-General_Concept
chip	O
,	O
a	O
storage	O
control	O
unit	O
chip	O
,	O
and	O
two	O
or	O
four	O
data	O
cache	O
unit	O
chips	O
.	O
</s>
<s>
The	O
chips	O
are	O
packaged	O
in	O
a	O
ceramic	O
multi-chip	B-Algorithm
module	I-Algorithm
(	O
MCM	O
)	O
that	O
measures	O
64mm	O
by	O
64mm	O
.	O
</s>
<s>
An	O
improved	O
version	O
of	O
the	O
POWER2	B-General_Concept
optimized	O
for	O
transaction	B-General_Concept
processing	I-General_Concept
was	O
introduced	O
in	O
May	O
1994	O
as	O
the	O
POWER2+	B-General_Concept
.	O
</s>
<s>
Transaction	B-General_Concept
processing	I-General_Concept
workloads	O
benefited	O
from	O
the	O
addition	O
of	O
a	O
L2	O
cache	O
with	O
capacities	O
of	O
512KB	O
,	O
1MB	O
and	O
2MB	O
.	O
</s>
<s>
The	O
cache	O
was	O
connected	O
to	O
the	O
POWER2+	B-General_Concept
via	O
a	O
64	O
-	O
(	O
for	O
low-end	O
systems	O
)	O
or	O
128-bit	O
bus	O
(	O
for	O
high-end	O
systems	O
)	O
.	O
</s>
<s>
The	O
POWER2+	B-General_Concept
has	O
a	O
narrower	O
64	O
-	O
or	O
128-bit	O
memory	O
bus	O
and	O
a	O
smaller	O
64	O
or	O
128KB	O
data	O
cache	O
.	O
</s>
<s>
A	O
goal	O
for	O
the	O
six-chip	O
configuration	O
was	O
to	O
reduce	O
cost	O
,	O
and	O
therefore	O
the	O
chips	O
are	O
packaged	O
in	O
a	O
solder	B-Algorithm
ball	I-Algorithm
connect	O
(	O
SBC	O
)	O
package	O
instead	O
of	O
a	O
MCM	O
.	O
</s>
<s>
POWER2	B-General_Concept
Super	O
Chip	O
(	O
P2SC	O
)	O
was	O
released	O
in	O
October	O
1996	O
as	O
the	O
successor	O
of	O
the	O
POWER2	B-General_Concept
.	O
</s>
<s>
It	O
was	O
a	O
single-chip	O
implementation	O
of	O
the	O
eight-chip	O
POWER2	B-General_Concept
,	O
integrating	O
15	O
million	O
transistors	O
on	O
a	O
335mm2	O
die	O
manufactured	O
in	O
IBM	O
's	O
0.29μm	O
five-layer	O
metal	O
CMOS-6S	O
process	O
.	O
</s>
<s>
The	O
first	O
version	O
ran	O
at	O
120	O
or	O
135MHz	O
,	O
nearly	O
twice	O
as	O
fast	O
as	O
the	O
POWER2	B-General_Concept
at	O
71.5MHz	O
,	O
with	O
the	O
memory	O
and	O
I/O	O
buses	O
running	O
at	O
half	O
speed	O
to	O
support	O
the	O
higher	O
clock	O
frequency	O
.	O
</s>
<s>
The	O
P2SC	O
was	O
not	O
a	O
complete	O
copy	O
of	O
the	O
POWER2	B-General_Concept
,	O
the	O
L1	O
data	O
cache	O
and	O
data	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	O
)	O
capacities	O
were	O
halved	O
to	O
128KB	O
and	O
256	O
entries	O
,	O
respectively	O
,	O
and	O
a	O
rarely	O
used	O
feature	O
that	O
locked	O
entries	O
in	O
the	O
TLB	O
was	O
not	O
implemented	O
in	O
order	O
to	O
fit	O
the	O
original	O
design	O
onto	O
a	O
single	O
die	O
.	O
</s>
<s>
The	O
P2SC	O
was	O
succeeded	O
by	O
the	O
POWER3	B-General_Concept
as	O
IBM	O
's	O
flagship	O
microprocessor	O
on	O
the	O
RS/6000	B-Device
line	O
in	O
1998	O
.	O
</s>
<s>
A	O
notable	O
use	O
of	O
the	O
P2SC	O
was	O
the	O
30-node	O
IBM	B-General_Concept
Deep	I-General_Concept
Blue	I-General_Concept
supercomputer	O
that	O
beat	O
world	O
champion	O
Garry	O
Kasparov	O
at	O
chess	O
in	O
1997	O
.	O
</s>
<s>
However	O
,	O
the	O
computer	O
's	O
chess-playing	O
capabilities	O
were	O
a	O
result	O
of	O
its	O
expert	B-Application
system	I-Application
running	O
on	O
custom	O
VLSI	O
chips	O
,	O
rather	O
than	O
the	O
P2SCs	O
.	O
</s>
