<s>
The	O
POWER1	B-General_Concept
is	O
a	O
multi-chip	O
CPU	B-General_Concept
developed	O
and	O
fabricated	B-Architecture
by	O
IBM	O
that	O
implemented	O
the	O
POWER	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
.	O
</s>
<s>
It	O
was	O
originally	O
known	O
as	O
the	O
RISC	B-Device
System/6000	I-Device
CPU	B-General_Concept
or	O
,	O
when	O
in	O
an	O
abbreviated	O
form	O
,	O
the	O
RS/6000	B-Device
CPU	B-General_Concept
,	O
before	O
introduction	O
of	O
successors	O
required	O
the	O
original	O
name	O
to	O
be	O
replaced	O
with	O
one	O
that	O
used	O
the	O
same	O
naming	O
scheme	O
(	O
POWERn	O
)	O
as	O
its	O
successors	O
in	O
order	O
to	O
differentiate	O
it	O
from	O
the	O
newer	O
designs	O
.	O
</s>
<s>
The	O
POWER1	B-General_Concept
was	O
introduced	O
in	O
1990	O
,	O
with	O
the	O
introduction	O
of	O
the	O
IBM	B-Device
RS/6000	I-Device
POWERserver	O
servers	B-Application
and	O
POWERstation	O
workstations	B-Device
,	O
which	O
featured	O
the	O
POWER1	B-General_Concept
clocked	O
at	O
20	O
,	O
25	O
or	O
30	O
MHz	O
.	O
</s>
<s>
The	O
POWER1	B-General_Concept
received	O
two	O
upgrades	O
,	O
one	O
in	O
1991	O
,	O
with	O
the	O
introduction	O
of	O
the	O
POWER1+	O
and	O
in	O
1992	O
,	O
with	O
the	O
introduction	O
of	O
POWER1++	O
.	O
</s>
<s>
These	O
upgraded	O
versions	O
were	O
clocked	O
higher	O
than	O
the	O
original	O
POWER1	B-General_Concept
,	O
made	O
possible	O
by	O
improved	O
semiconductor	B-Architecture
processes	I-Architecture
.	O
</s>
<s>
The	O
POWER1+	O
was	O
clocked	O
slightly	O
higher	O
than	O
the	O
original	O
POWER1	B-General_Concept
,	O
at	O
frequencies	O
of	O
25	O
,	O
33	O
and	O
41MHz	O
,	O
while	O
the	O
POWER1++	O
took	O
the	O
microarchitecture	O
to	O
its	O
highest	O
frequencies	O
—	O
25	O
,	O
33	O
,	O
41.6	O
,	O
45	O
,	O
50	O
and	O
62.5MHz	O
.	O
</s>
<s>
In	O
September	O
1993	O
,	O
the	O
POWER1	B-General_Concept
and	O
its	O
variants	O
was	O
succeeded	O
by	O
the	O
POWER2	B-General_Concept
(	O
known	O
briefly	O
as	O
the	O
"	O
RIOS2	O
"	O
)	O
,	O
an	O
evolution	O
of	O
the	O
POWER1	B-General_Concept
microarchitecture	O
.	O
</s>
<s>
The	O
direct	O
derivatives	O
of	O
the	O
POWER1	B-General_Concept
are	O
the	O
RISC	B-Device
Single	I-Device
Chip	I-Device
(	O
RSC	O
)	O
,	O
feature-reduced	O
single-chip	O
variant	O
for	O
entry-level	O
RS/6000	B-Device
systems	O
,	O
and	O
the	O
RAD6000	B-Device
,	O
a	O
radiation-hardened	O
variant	O
of	O
the	O
RSC	O
for	O
space	O
applications	O
.	O
</s>
<s>
An	O
indirect	O
derivative	O
of	O
the	O
POWER1	B-General_Concept
is	O
the	O
PowerPC	B-Architecture
601	O
,	O
a	O
feature-reduced	O
variant	O
of	O
the	O
RSC	O
intended	O
for	O
consumer	O
applications	O
.	O
</s>
<s>
The	O
POWER1	B-General_Concept
is	O
notable	O
as	O
it	O
represented	O
a	O
number	O
of	O
firsts	O
for	O
IBM	O
and	O
computing	O
in	O
general	O
.	O
</s>
<s>
It	O
was	O
IBM	O
's	O
first	O
RISC	B-Architecture
processor	I-Architecture
intended	O
for	O
high-end	O
applications	O
(	O
the	O
ROMP	B-Device
was	O
considered	O
a	O
commercial	O
failure	O
and	O
was	O
not	O
used	O
in	O
high-end	O
workstations	B-Device
)	O
,	O
it	O
was	O
the	O
first	O
to	O
implement	O
the	O
then	O
new	O
POWER	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
and	O
it	O
was	O
IBM	O
's	O
first	O
successful	O
RISC	B-Architecture
processor	I-Architecture
.	O
</s>
<s>
For	O
computing	O
firsts	O
,	O
the	O
POWER1	B-General_Concept
would	O
be	O
known	O
for	O
being	O
the	O
first	O
CPU	B-General_Concept
to	O
implement	O
some	O
form	O
of	O
register	B-Architecture
renaming	I-Architecture
and	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
a	O
technique	O
that	O
improves	O
the	O
performance	O
of	O
superscalar	B-General_Concept
processors	I-General_Concept
but	O
was	O
previously	O
reserved	O
for	O
mainframes	B-Architecture
.	O
</s>
<s>
The	O
POWER1	B-General_Concept
was	O
also	O
the	O
origin	O
for	O
the	O
highly	O
successful	O
families	O
of	O
POWER	B-Architecture
,	O
PowerPC	B-Architecture
and	O
Power	B-Architecture
ISA	I-Architecture
processors	O
that	O
followed	O
it	O
,	O
measuring	O
in	O
hundreds	O
of	O
different	O
implementations	O
.	O
</s>
<s>
The	O
open	O
source	O
GCC	B-Application
compiler	I-Application
removed	O
support	O
for	O
POWER1	B-General_Concept
(	O
RIOS	O
)	O
and	O
POWER2	B-General_Concept
(	O
RIOS2	O
)	O
in	O
the	O
4.5	O
release	O
.	O
</s>
<s>
The	O
POWER1	B-General_Concept
is	O
a	O
32-bit	O
two-way	O
superscalar	B-General_Concept
CPU	B-General_Concept
.	O
</s>
<s>
It	O
contains	O
three	O
major	O
execution	O
units	O
,	O
a	O
fixed-point	B-General_Concept
unit	I-General_Concept
(	O
FXU	O
)	O
,	O
a	O
branch	B-General_Concept
unit	I-General_Concept
(	O
BPU	O
)	O
and	O
a	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
.	O
</s>
<s>
Although	O
the	O
POWER1	B-General_Concept
is	O
a	O
32-bit	O
CPU	B-General_Concept
with	O
a	O
32-bit	O
physical	B-General_Concept
address	I-General_Concept
,	O
its	O
virtual	B-General_Concept
address	I-General_Concept
is	O
52	O
bits	O
long	O
.	O
</s>
<s>
The	O
larger	O
virtual	B-General_Concept
address	I-General_Concept
space	I-General_Concept
was	O
chosen	O
because	O
it	O
was	O
beneficial	O
for	O
the	O
performance	O
of	O
applications	O
,	O
allowing	O
each	O
one	O
to	O
have	O
a	O
large	O
4	O
GB	O
address	B-General_Concept
range	I-General_Concept
.	O
</s>
<s>
The	O
POWER1	B-General_Concept
is	O
a	O
big-endian	O
CPU	B-General_Concept
that	O
uses	O
a	O
Harvard	B-Architecture
style	I-Architecture
cache	B-General_Concept
hierarchy	O
with	O
separate	O
instruction	O
and	O
data	B-General_Concept
caches	I-General_Concept
.	O
</s>
<s>
The	O
instruction	O
cache	B-General_Concept
,	O
referred	O
to	O
as	O
the	O
"	O
I-cache	O
"	O
by	O
IBM	O
,	O
is	O
8	O
KB	O
in	O
size	O
and	O
is	O
two-way	O
set	O
associative	O
with	O
a	O
line	O
size	O
of	O
64	O
bytes	O
.	O
</s>
<s>
The	O
I-cache	O
is	O
located	O
on	O
the	O
ICU	O
chip	O
.	O
</s>
<s>
The	O
data	B-General_Concept
cache	I-General_Concept
,	O
referred	O
to	O
as	O
the	O
"	O
D-cache	O
"	O
by	O
IBM	O
,	O
is	O
32	O
KB	O
in	O
size	O
for	O
RIOS.9	O
configurations	O
and	O
64	O
KB	O
in	O
size	O
for	O
RIOS-1	O
configurations	O
.	O
</s>
<s>
The	O
D-cache	O
is	O
four-way	O
set	O
associative	O
with	O
a	O
line	O
size	O
of	O
128	O
bytes	O
.	O
</s>
<s>
The	O
D-cache	O
employs	O
a	O
store-back	O
scheme	O
,	O
where	O
data	O
that	O
is	O
to	O
be	O
stored	O
is	O
written	O
to	O
the	O
cache	B-General_Concept
instead	O
of	O
the	O
memory	B-Architecture
in	O
order	O
to	O
reduce	O
the	O
number	O
of	O
writes	O
destined	O
for	O
the	O
memory	B-Architecture
.	O
</s>
<s>
The	O
store-back	O
scheme	O
is	O
used	O
to	O
prevent	O
the	O
CPU	B-General_Concept
from	O
monopolizing	O
access	O
to	O
the	O
memory	B-Architecture
.	O
</s>
<s>
Although	O
the	O
POWER1	B-General_Concept
was	O
a	O
high-end	O
design	O
,	O
it	O
was	O
not	O
capable	O
of	O
multiprocessing	B-Operating_System
,	O
and	O
as	O
such	O
was	O
disadvantaged	O
,	O
as	O
the	O
only	O
way	O
performance	O
could	O
be	O
improved	O
was	O
by	O
clocking	O
the	O
CPU	B-General_Concept
higher	O
,	O
which	O
was	O
difficult	O
to	O
do	O
with	O
such	O
a	O
large	O
multi-chip	O
design	O
.	O
</s>
<s>
IBM	O
used	O
clustering	O
to	O
overcome	O
this	O
disadvantage	O
in	O
POWER1	B-General_Concept
systems	O
,	O
allowing	O
them	O
to	O
effectively	O
function	O
as	O
if	O
they	O
were	O
multiprocessing	B-Operating_System
systems	O
,	O
a	O
concept	O
proven	O
by	O
the	O
popularity	O
of	O
SP1	B-Operating_System
supercomputers	I-Operating_System
based	O
on	O
the	O
POWER1	B-General_Concept
.	O
</s>
<s>
As	O
the	O
POWER1	B-General_Concept
was	O
the	O
basis	O
of	O
the	O
POWER2	B-General_Concept
and	O
P2SC	O
microprocessors	O
,	O
the	O
lack	O
of	O
multiprocessing	B-Operating_System
was	O
passed	O
on	O
to	O
these	O
later	O
POWER	B-Architecture
processors	O
.	O
</s>
<s>
Multiprocessing	B-Operating_System
was	O
not	O
supported	O
until	O
the	O
introduction	O
of	O
the	O
POWER3	B-General_Concept
in	O
1998	O
.	O
</s>
<s>
The	O
POWER1	B-General_Concept
is	O
a	O
multi-chip	O
CPU	B-General_Concept
built	O
from	O
separate	O
chips	O
that	O
are	O
connected	O
to	O
each	O
other	O
by	O
buses	B-General_Concept
.	O
</s>
<s>
The	O
POWER1	B-General_Concept
consists	O
of	O
an	O
instruction-cache	B-General_Concept
unit	O
(	O
ICU	O
)	O
,	O
a	O
fixed-point	B-General_Concept
unit	I-General_Concept
(	O
FXU	O
)	O
,	O
a	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
,	O
a	O
number	O
of	O
data-cache	B-General_Concept
units	O
(	O
DCU	O
)	O
,	O
a	O
storage-control	B-General_Concept
unit	O
(	O
SCU	O
)	O
and	O
an	O
I/O	B-General_Concept
unit	O
.	O
</s>
<s>
The	O
RIOS-1	O
configuration	O
has	O
four	O
DCUs	O
,	O
the	O
intended	O
amount	O
,	O
and	O
was	O
clocked	O
at	O
up	O
to	O
40MHz	O
,	O
whereas	O
the	O
RIOS.9	O
CPU	B-General_Concept
had	O
two	O
DCUs	O
and	O
was	O
clocked	O
at	O
lower	O
frequencies	O
.	O
</s>
<s>
The	O
chips	O
are	O
mounted	O
on	O
the	O
“	O
CPU	B-General_Concept
planar	O
”	O
,	O
a	O
printed	O
circuit	O
board	O
(	O
PCB	O
)	O
,	O
using	O
through-hole	O
technology	O
.	O
</s>
<s>
Due	O
to	O
the	O
large	O
number	O
of	O
chips	O
with	O
wide	O
buses	B-General_Concept
,	O
the	O
PCB	O
has	O
eight	O
planes	O
for	O
routing	O
wires	O
,	O
four	O
for	O
power	B-Architecture
and	O
ground	O
and	O
four	O
for	O
signals	O
.	O
</s>
<s>
There	O
are	O
two	O
signal	O
planes	O
on	O
each	O
side	O
of	O
the	O
board	O
,	O
while	O
the	O
four	O
power	B-Architecture
and	O
ground	O
planes	O
are	O
in	O
the	O
center	O
.	O
</s>
<s>
The	O
chips	O
that	O
make	O
up	O
the	O
POWER1	B-General_Concept
are	O
fabricated	B-Architecture
in	O
a	O
1.0µm	O
CMOS	B-Device
process	O
with	O
three	O
layers	O
of	O
interconnect	B-General_Concept
.	O
</s>
<s>
The	O
chips	O
are	O
packaged	O
in	O
ceramic	B-Algorithm
pin	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
CPGA	O
)	O
packages	O
that	O
can	O
have	O
up	O
to	O
300	O
pins	O
and	O
dissipate	O
a	O
maximum	O
of	O
4	O
W	O
of	O
heat	O
each	O
.	O
</s>
<s>
The	O
total	O
number	O
of	O
transistors	B-Application
featured	O
by	O
the	O
POWER1	B-General_Concept
,	O
assuming	O
that	O
it	O
is	O
a	O
RIOS-1	O
configuration	O
,	O
is	O
6.9	O
million	O
,	O
with	O
2.04	O
million	O
used	O
for	O
logic	O
and	O
4.86	O
million	O
used	O
for	O
memory	B-Architecture
.	O
</s>
<s>
The	O
ICU	O
contains	O
the	O
instruction	O
cache	B-General_Concept
,	O
referred	O
to	O
as	O
the	O
"	O
I-cache	O
"	O
by	O
IBM	O
and	O
the	O
branch	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
BPU	O
)	O
.	O
</s>
<s>
The	O
BPU	O
contains	O
the	O
program	B-General_Concept
counter	I-General_Concept
,	O
the	O
condition	O
code	O
register	O
and	O
a	O
loop	O
register	O
.	O
</s>
<s>
The	O
ICU	O
contains	O
0.75	O
million	O
transistors	B-Application
with	O
0.2	O
million	O
used	O
for	O
logic	O
and	O
0.55	O
million	O
used	O
for	O
SRAM	B-Architecture
.	O
</s>
<s>
Speculative	O
branches	B-General_Concept
were	O
also	O
supported	O
by	O
using	O
a	O
prediction	O
bit	O
in	O
the	O
branch	B-General_Concept
instructions	I-General_Concept
,	O
with	O
the	O
results	O
discarded	O
before	O
being	O
saved	O
if	O
the	O
branch	O
was	O
not	O
taken	O
.	O
</s>
<s>
Consequently	O
,	O
subroutine	O
calls	O
and	O
interrupts	B-Application
are	O
dealt	O
with	O
without	O
incurring	O
branch	O
penalties	O
.	O
</s>
<s>
The	O
condition	O
code	O
register	O
has	O
eight	O
field	O
sets	O
,	O
with	O
the	O
first	O
two	O
reserved	O
for	O
fixed	O
and	O
floating	O
point	O
instructions	O
and	O
the	O
seventh	O
for	O
vector	B-Device
instructions	I-Device
.	O
</s>
<s>
The	O
FXU	O
is	O
responsible	O
for	O
decoding	O
and	O
executing	O
all	O
fixed-point	O
instructions	O
and	O
floating-point	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
.	O
</s>
<s>
For	O
execution	O
,	O
the	O
FXU	O
contains	O
the	O
POWER1	B-General_Concept
's	O
fixed-point	O
register	O
file	O
,	O
an	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
)	O
for	O
general	O
instructions	O
,	O
and	O
a	O
dedicated	O
fixed-point	O
multiply	O
and	O
divide	O
unit	O
.	O
</s>
<s>
It	O
also	O
contains	O
instruction	O
buffers	O
that	O
receive	O
both	O
fixed	O
-	O
and	O
floating-point	O
instructions	O
from	O
the	O
ICU	O
,	O
passing	O
on	O
the	O
floating-point	O
instructions	O
to	O
the	O
FPU	O
,	O
and	O
a	O
128-entry	O
two-way	O
set-associative	O
D-TLB	O
for	O
address	O
translation	O
.	O
</s>
<s>
The	O
FXU	O
contains	O
approximately	O
0.5	O
million	O
transistors	B-Application
,	O
with	O
0.25	O
million	O
used	O
for	O
logic	O
and	O
0.25	O
used	O
for	O
memory	B-Architecture
,	O
on	O
a	O
die	O
measuring	O
approximately	O
160mm²	O
.	O
</s>
<s>
The	O
POWER1	B-General_Concept
's	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
executes	O
floating-point	O
instructions	O
issue	O
by	O
the	O
ICU	O
.	O
</s>
<s>
The	O
FPU	O
is	O
pipelined	B-General_Concept
and	O
can	O
execute	O
single	O
precision	O
(	O
32-bit	O
)	O
and	O
double	O
precision	O
(	O
64-bit	O
)	O
instructions	O
.	O
</s>
<s>
It	O
is	O
capable	O
of	O
performing	O
multiply-add	B-Algorithm
instructions	O
,	O
which	O
contributed	O
to	O
the	O
POWER1	B-General_Concept
's	O
high	O
floating	O
point	O
performance	O
.	O
</s>
<s>
In	O
most	O
processors	O
,	O
a	O
multiply	O
and	O
an	O
add	O
,	O
which	O
is	O
common	O
in	O
technical	O
and	O
scientific	O
floating-point	O
code	O
,	O
cannot	O
be	O
executed	O
in	O
one	O
cycle	O
,	O
as	O
in	O
the	O
POWER1	B-General_Concept
.	O
</s>
<s>
Use	O
of	O
fused	O
multiply	B-Algorithm
–	I-Algorithm
add	I-Algorithm
also	O
means	O
that	O
the	O
data	O
is	O
only	O
rounded	O
once	O
,	O
improving	O
the	O
precision	O
of	O
the	O
result	O
slightly	O
.	O
</s>
<s>
The	O
POWER1	B-General_Concept
has	O
a	O
64	O
KB	O
data	B-General_Concept
cache	I-General_Concept
implemented	O
through	O
four	O
identical	O
data-cache	B-General_Concept
units	O
(	O
DCU	O
)	O
,	O
each	O
containing	O
16	O
KB	O
of	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
The	O
cache	B-General_Concept
and	O
the	O
buses	B-General_Concept
that	O
connect	O
the	O
DCU	O
to	O
the	O
other	O
chips	O
are	O
ECC	O
protected	O
.	O
</s>
<s>
The	O
DCUs	O
also	O
provide	O
the	O
interface	O
to	O
the	O
memory	B-Architecture
.	O
</s>
<s>
If	O
two	O
DCUs	O
are	O
present	O
(	O
RIOS.9	O
configuration	O
)	O
,	O
the	O
memory	B-Architecture
bus	O
is	O
64	O
bits	O
wide	O
,	O
and	O
if	O
four	O
DCUs	O
are	O
present	O
(	O
RIOS-1	O
configuration	O
)	O
,	O
the	O
memory	B-Architecture
bus	O
is	O
128	O
bits	O
wide	O
.	O
</s>
<s>
The	O
memory	B-Architecture
interface	O
portion	O
of	O
the	O
DCUs	O
provide	O
three	O
features	O
that	O
improves	O
the	O
reliability	O
and	O
availability	O
of	O
the	O
memory	B-Architecture
:	O
memory	B-General_Concept
scrubbing	I-General_Concept
,	O
ECC	O
and	O
bit	O
steering	O
.	O
</s>
<s>
Each	O
DCU	O
contains	O
approximately	O
1.125	O
million	O
transistors	B-Application
,	O
with	O
0.175	O
million	O
used	O
for	O
logic	O
and	O
0.95	O
million	O
used	O
for	O
SRAM	B-Architecture
,	O
on	O
a	O
die	O
measuring	O
approximately	O
130mm²	O
(	O
11.3	O
×	O
11.3mm	O
)	O
.	O
</s>
<s>
The	O
POWER1	B-General_Concept
is	O
controlled	O
by	O
the	O
SCU	O
chip	O
.	O
</s>
<s>
All	O
communications	O
between	O
the	O
ICU	O
,	O
FXU	O
and	O
DCU	O
chips	O
as	O
well	O
as	O
the	O
memory	B-Architecture
and	O
I/O	B-General_Concept
devices	I-General_Concept
is	O
arbitrated	O
by	O
the	O
SCU	O
.	O
</s>
<s>
Although	O
the	O
DCUs	O
provide	O
the	O
means	O
to	O
perform	O
memory	B-General_Concept
scrubbing	I-General_Concept
,	O
it	O
is	O
the	O
SCU	O
that	O
controls	O
the	O
process	O
.	O
</s>
<s>
The	O
SCU	O
contains	O
approximately	O
0.23	O
million	O
transistors	B-Application
,	O
all	O
of	O
them	O
for	O
logic	O
,	O
on	O
a	O
die	O
measuring	O
approximately	O
130mm²	O
.	O
</s>
<s>
The	O
POWER1	B-General_Concept
's	O
I/O	B-General_Concept
interfaces	I-General_Concept
are	O
implemented	O
by	O
the	O
I/O	B-General_Concept
unit	O
,	O
which	O
contains	O
an	O
I/O	B-General_Concept
channel	O
controller	O
(	O
IOCC	O
)	O
and	O
two	O
serial	B-Protocol
link	I-Protocol
adapters	O
(	O
SLAs	O
)	O
.	O
</s>
<s>
The	O
IOCC	O
implements	O
the	O
Micro	B-Device
Channel	I-Device
interface	O
and	O
controls	O
both	O
I/O	B-General_Concept
and	O
DMA	B-General_Concept
transactions	O
between	O
the	O
Micro	B-Device
Channel	I-Device
adapters	O
and	O
the	O
system	O
memory	B-Architecture
.	O
</s>
<s>
The	O
two	O
SLAs	O
each	O
implement	O
a	O
serial	O
fibre	B-Architecture
optic	I-Architecture
link	O
,	O
which	O
are	O
intended	O
to	O
connect	O
RS/6000	B-Device
systems	O
together	O
.	O
</s>
<s>
The	O
optical	O
links	O
were	O
not	O
supported	O
at	O
the	O
time	O
of	O
the	O
RS/6000	B-Device
'	O
s	O
release	O
.	O
</s>
<s>
The	O
I/O	B-General_Concept
unit	O
contains	O
approximately	O
0.5	O
million	O
transistors	B-Application
,	O
with	O
0.3	O
million	O
used	O
for	O
logic	O
and	O
0.2	O
million	O
used	O
for	O
memory	B-Architecture
,	O
on	O
a	O
die	O
measuring	O
approximately	O
160mm²	O
.	O
</s>
