<s>
PMOS	O
or	O
pMOS	B-Algorithm
logic	I-Algorithm
(	O
from	O
p-channel	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
)	O
is	O
a	O
family	O
of	O
digital	O
circuits	O
based	O
on	O
p-channel	O
,	O
enhancement	B-Algorithm
mode	I-Algorithm
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
field-effect	I-Architecture
transistors	I-Architecture
(	O
MOSFETs	B-Architecture
)	O
.	O
</s>
<s>
In	O
the	O
late	O
1960s	O
and	O
early	O
1970s	O
,	O
PMOS	B-Algorithm
logic	I-Algorithm
was	O
the	O
dominant	O
semiconductor	O
technology	O
for	O
large-scale	O
integrated	O
circuits	O
before	O
being	O
superseded	O
by	O
NMOS	B-Algorithm
and	O
CMOS	B-Device
devices	O
.	O
</s>
<s>
Mohamed	O
Atalla	O
and	O
Dawon	O
Kahng	O
manufactured	O
the	O
first	O
working	O
MOSFET	B-Architecture
at	O
Bell	O
Labs	O
in	O
1959	O
.	O
</s>
<s>
They	O
fabricated	O
both	O
PMOS	O
and	O
NMOS	B-Algorithm
devices	O
but	O
only	O
the	O
PMOS	O
devices	O
were	O
working	O
.	O
</s>
<s>
It	O
would	O
be	O
more	O
than	O
a	O
decade	O
before	O
contaminants	O
in	O
the	O
manufacturing	O
process	O
(	O
particularly	O
sodium	O
)	O
could	O
be	O
managed	O
well	O
enough	O
to	O
manufacture	O
practical	O
NMOS	B-Algorithm
devices	O
.	O
</s>
<s>
Compared	O
to	O
the	O
bipolar	O
junction	O
transistor	O
,	O
the	O
only	O
other	O
device	O
available	O
at	O
the	O
time	O
for	O
use	O
in	O
an	O
integrated	O
circuit	O
,	O
the	O
MOSFET	B-Architecture
offers	O
a	O
number	O
of	O
advantages	O
:	O
</s>
<s>
Given	O
semiconductor	B-Architecture
device	I-Architecture
fabrication	I-Architecture
processes	O
of	O
similar	O
precision	O
,	O
a	O
MOSFET	B-Architecture
requires	O
only	O
10%	O
of	O
the	O
area	O
of	O
a	O
bipolar	O
junction	O
transistor	O
.	O
</s>
<s>
The	O
main	O
reason	O
is	O
that	O
the	O
MOSFET	B-Architecture
is	O
self-insulating	O
and	O
does	O
not	O
require	O
p	O
–	O
n	O
junction	O
isolation	O
from	O
neighboring	O
components	O
on	O
the	O
chip	O
.	O
</s>
<s>
A	O
MOSFET	B-Architecture
requires	O
fewer	O
process	O
steps	O
and	O
is	O
therefore	O
simpler	O
and	O
cheaper	O
to	O
manufacture	O
(	O
one	O
diffusion	O
doping	O
step	O
compared	O
to	O
four	O
for	O
a	O
bipolar	O
process	O
)	O
.	O
</s>
<s>
Since	O
there	O
is	O
no	O
static	O
gate	O
current	O
for	O
a	O
MOSFET	B-Architecture
,	O
the	O
power	O
consumption	O
of	O
an	O
integrated	O
circuit	O
based	O
on	O
MOSFETs	B-Architecture
can	O
be	O
lower	O
.	O
</s>
<s>
The	O
high	O
threshold	O
voltage	O
of	O
early	O
MOSFETs	B-Architecture
led	O
to	O
a	O
higher	O
minimum	O
power-supply	O
voltage	O
(	O
-24V	O
to	O
-28V	O
)	O
.	O
</s>
<s>
General	O
Microelectronics	O
introduced	O
the	O
first	O
commercial	O
PMOS	O
circuit	O
in	O
1964	O
,	O
a	O
20-bit	O
shift	O
register	O
with	O
120	O
MOSFETs	B-Architecture
–	O
at	O
the	O
time	O
an	O
incredible	O
level	O
of	O
integration	O
.	O
</s>
<s>
Other	O
companies	O
continued	O
to	O
manufacture	O
PMOS	O
circuits	O
such	O
as	O
large	O
shift	O
registers	O
(	O
General	O
Instrument	O
)	O
or	O
the	O
analogue	O
multiplexer	B-Protocol
3705	O
(	O
Fairchild	O
Semiconductor	O
)	O
which	O
were	O
not	O
feasible	O
in	O
bipolar	O
technologies	O
of	O
the	O
day	O
.	O
</s>
<s>
Tom	O
Klein	O
and	O
Federico	O
Faggin	O
at	O
Fairchild	O
Semiconductor	O
improved	O
the	O
self-aligned	O
gate	O
process	O
to	O
make	O
it	O
commercially	O
viable	O
,	O
resulting	O
in	O
the	O
release	O
of	O
the	O
analogue	O
multiplexer	B-Protocol
3708	O
as	O
the	O
first	O
silicon-gate	O
integrated	O
circuit	O
.	O
</s>
<s>
The	O
self-aligned	O
gate	O
process	O
allowed	O
tighter	O
manufacturing	O
tolerances	O
and	O
thus	O
both	O
smaller	O
MOSFETs	B-Architecture
and	O
reduced	O
,	O
consistent	O
gate	O
capacitances	O
.	O
</s>
<s>
Because	O
of	O
the	O
lower	O
power	O
supply	O
voltage	O
,	O
silicon	O
gate	O
PMOS	B-Algorithm
logic	I-Algorithm
is	O
often	O
referred	O
to	O
as	O
low-voltage	O
PMOS	O
in	O
contrast	O
to	O
the	O
older	O
,	O
metal-gate	O
PMOS	O
as	O
high-voltage	O
PMOS	O
.	O
</s>
<s>
Intel	O
introduced	O
its	O
first	O
PMOS	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
with	O
a	O
capacity	O
of	O
256	O
bit	O
,	O
the	O
Intel	O
1101	O
,	O
in	O
1969	O
.	O
</s>
<s>
The	O
1024-bit	O
dynamic	O
random-access	O
memory	O
Intel	B-General_Concept
1103	I-General_Concept
followed	O
in	O
1970	O
.	O
</s>
<s>
Intel	O
introduced	O
its	O
first	O
PMOS	O
microprocessor	B-Architecture
,	O
the	O
Intel	B-General_Concept
4004	I-General_Concept
,	O
in	O
1971	O
.	O
</s>
<s>
Most	O
early	B-General_Concept
microprocessors	I-General_Concept
were	O
manufactured	O
in	O
PMOS	O
technology	O
:	O
4040	B-General_Concept
and	O
8008	B-General_Concept
from	O
Intel	O
;	O
IMP-16	B-Device
,	O
PACE	B-Device
and	O
SC/MP	B-Device
from	O
National	O
Semiconductor	O
;	O
TMS1000	B-Device
from	O
Texas	O
Instruments	O
;	O
PPS-4	B-General_Concept
and	O
PPS-8	O
from	O
Rockwell	O
International	O
.	O
</s>
<s>
There	O
are	O
several	O
commercial	O
firsts	O
in	O
this	O
list	O
of	O
microprocessors	B-Architecture
:	O
the	O
first	O
4-bit	O
microprocessor	B-Architecture
(	O
4004	B-General_Concept
)	O
,	O
the	O
first	O
8-bit	O
microprocessor	B-Architecture
(	O
8008	B-General_Concept
)	O
,	O
the	O
first	O
single-chip	O
16-bit	O
microprocessor	B-Architecture
(	O
PACE	B-Device
)	O
,	O
and	O
the	O
first	O
single-chip	O
4-bit	O
microcontroller	O
(	O
TMS1000	B-Device
;	O
RAM	O
and	O
ROM	B-Device
on	O
the	O
same	O
chip	O
as	O
the	O
CPU	B-General_Concept
)	O
.	O
</s>
<s>
By	O
1972	O
,	O
NMOS	B-Algorithm
technology	O
had	O
finally	O
been	O
developed	O
to	O
the	O
point	O
where	O
it	O
could	O
be	O
used	O
in	O
commercial	O
products	O
.	O
</s>
<s>
As	O
the	O
electron	O
mobility	O
in	O
the	O
n-type	O
channel	O
of	O
NMOS	B-Algorithm
MOSFETs	B-Architecture
is	O
about	O
three	O
times	O
that	O
of	O
the	O
hole	O
mobility	O
in	O
the	O
p-type	O
channel	O
of	O
PMOS	O
MOSFETS	B-Architecture
,	O
NMOS	B-Algorithm
logic	I-Algorithm
allows	O
for	O
an	O
increased	O
switching	O
speed	O
.	O
</s>
<s>
For	O
this	O
reason	O
NMOS	B-Algorithm
logic	I-Algorithm
quickly	O
began	O
to	O
replace	O
PMOS	B-Algorithm
logic	I-Algorithm
.	O
</s>
<s>
By	O
the	O
late	O
1970s	O
,	O
NMOS	B-Algorithm
microprocessors	B-Architecture
had	O
overtaken	O
PMOS	O
processors	O
.	O
</s>
<s>
PMOS	B-Algorithm
logic	I-Algorithm
remained	O
in	O
use	O
for	O
a	O
while	O
due	O
to	O
its	O
low	O
cost	O
and	O
relatively	O
high	O
level	O
of	O
integration	O
for	O
applications	O
such	O
as	O
simple	O
calculators	O
and	O
clocks	O
.	O
</s>
<s>
CMOS	B-Device
technology	O
promised	O
a	O
drastically	O
lower	O
power	O
consumption	O
than	O
either	O
PMOS	O
or	O
NMOS	B-Algorithm
.	O
</s>
<s>
Even	O
though	O
a	O
CMOS	B-Device
circuit	O
had	O
been	O
proposed	O
already	O
in	O
1963	O
by	O
Frank	O
Wanlass	O
and	O
commercial	O
4000	O
series	O
CMOS	B-Device
integrated	O
circuits	O
had	O
entered	O
production	O
in	O
1968	O
,	O
CMOS	B-Device
remained	O
complex	O
to	O
manufacture	O
and	O
allowed	O
neither	O
the	O
integration	O
level	O
of	O
PMOS	O
or	O
NMOS	B-Algorithm
nor	O
the	O
speed	O
of	O
NMOS	B-Algorithm
.	O
</s>
<s>
It	O
would	O
take	O
until	O
the	O
1980s	O
for	O
CMOS	B-Device
to	O
replace	O
NMOS	B-Algorithm
as	O
the	O
main	O
technology	O
for	O
microprocessors	B-Architecture
.	O
</s>
<s>
PMOS	O
circuits	O
have	O
a	O
number	O
of	O
disadvantages	O
compared	O
to	O
the	O
NMOS	B-Algorithm
and	O
CMOS	B-Device
alternatives	O
,	O
including	O
the	O
need	O
for	O
several	O
different	O
supply	O
voltages	O
(	O
both	O
positive	O
and	O
negative	O
)	O
,	O
high-power	O
dissipation	O
in	O
the	O
conducting	O
state	O
,	O
and	O
relatively	O
large	O
features	O
.	O
</s>
<s>
PMOS	O
uses	O
p-channel	O
( +	O
)	O
metal-oxide-semiconductor	B-Architecture
field	O
effect	O
transistors	O
(	O
MOSFETs	B-Architecture
)	O
to	O
implement	O
logic	O
gates	O
and	O
other	O
digital	O
circuits	O
.	O
</s>
<s>
PMOS	B-Architecture
transistors	I-Architecture
operate	O
by	O
creating	O
an	O
inversion	O
layer	O
in	O
an	O
n-type	O
transistor	O
body	O
.	O
</s>
<s>
Like	O
other	O
MOSFETs	B-Architecture
,	O
PMOS	B-Architecture
transistors	I-Architecture
have	O
four	O
modes	O
of	O
operation	O
:	O
cut-off	O
(	O
or	O
subthreshold	O
)	O
,	O
triode	O
,	O
saturation	O
(	O
sometimes	O
called	O
active	O
)	O
,	O
and	O
velocity	O
saturation	O
.	O
</s>
<s>
While	O
PMOS	B-Algorithm
logic	I-Algorithm
is	O
easy	O
to	O
design	O
and	O
manufacture	O
(	O
a	O
MOSFET	B-Architecture
can	O
be	O
made	O
to	O
operate	O
as	O
a	O
resistor	O
,	O
so	O
the	O
whole	O
circuit	O
can	O
be	O
made	O
with	O
PMOS	B-Architecture
FETs	I-Architecture
)	O
,	O
it	O
has	O
several	O
shortcomings	O
as	O
well	O
.	O
</s>
<s>
The	O
worst	O
problem	O
is	O
that	O
there	O
is	O
a	O
direct	O
current	O
(	O
DC	O
)	O
through	O
a	O
PMOS	B-Algorithm
logic	I-Algorithm
gate	O
when	O
the	O
so-called	O
"	O
pull-up	O
network	O
"	O
(	O
PUN	O
)	O
is	O
active	O
,	O
that	O
is	O
,	O
whenever	O
the	O
output	O
is	O
high	O
,	O
which	O
leads	O
to	O
static	O
power	O
dissipation	O
even	O
when	O
the	O
circuit	O
sits	O
idle	O
.	O
</s>
<s>
The	O
Intel	B-General_Concept
4004	I-General_Concept
PMOS	O
microprocessor	B-Architecture
,	O
however	O
,	O
uses	O
PMOS	B-Algorithm
logic	I-Algorithm
with	O
polysilicon	O
rather	O
than	O
metal	B-Algorithm
gates	I-Algorithm
allowing	O
a	O
smaller	O
voltage	O
differential	O
.	O
</s>
<s>
For	O
compatibility	O
with	O
TTL	B-General_Concept
signals	O
,	O
the	O
4004	B-General_Concept
uses	O
positive	O
supply	O
voltage	O
VSS	O
=	O
+5V	O
and	O
negative	O
supply	O
voltage	O
VDD	O
=	O
-10V	O
.	O
</s>
<s>
The	O
p-type	O
MOSFETs	B-Architecture
are	O
arranged	O
in	O
a	O
so-called	O
"	O
pull-up	O
network	O
"	O
(	O
PUN	O
)	O
between	O
the	O
logic	O
gate	O
output	O
and	O
positive	O
supply	O
voltage	O
,	O
while	O
a	O
resistor	O
is	O
placed	O
between	O
the	O
logic	O
gate	O
output	O
and	O
the	O
negative	O
supply	O
voltage	O
.	O
</s>
<s>
PMOS	O
gates	O
have	O
the	O
same	O
arrangement	O
as	O
NMOS	B-Algorithm
gates	O
if	O
all	O
the	O
voltages	O
are	O
reversed	O
.	O
</s>
<s>
Thus	O
,	O
for	O
active-high	O
logic	O
,	O
De	O
Morgan	O
's	O
laws	O
show	O
that	O
a	O
PMOS	O
NOR	O
gate	O
has	O
the	O
same	O
structure	O
as	O
an	O
NMOS	B-Algorithm
NAND	O
gate	O
and	O
vice	O
versa	O
.	O
</s>
