<s>
The	O
PIC	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
refers	O
to	O
the	O
set	O
of	O
instructions	O
that	O
Microchip	O
Technology	O
PIC	B-Architecture
or	O
dsPIC	O
microcontroller	B-Architecture
supports	O
.	O
</s>
<s>
The	O
instructions	O
are	O
usually	O
programmed	O
into	O
the	O
Flash	B-Device
memory	I-Device
of	O
the	O
processor	O
,	O
and	O
automatically	O
executed	O
by	O
the	O
microcontroller	B-Architecture
on	O
startup	O
.	O
</s>
<s>
PICmicro	B-Architecture
chips	O
have	O
a	O
Harvard	B-Architecture
architecture	I-Architecture
and	O
instruction	O
words	O
have	O
unusual	O
sizes	O
.	O
</s>
<s>
In	O
the	O
instruction	B-General_Concept
set	I-General_Concept
tables	O
that	O
follow	O
,	O
register	O
numbers	O
are	O
referred	O
to	O
as	O
"	O
f	O
"	O
,	O
while	O
constants	O
are	O
referred	O
to	O
as	O
"	O
k	O
"	O
.	O
</s>
<s>
The	O
"	O
d	O
"	O
bit	O
selects	O
the	O
destination	O
:	O
0	O
indicates	O
W	O
,	O
while	O
1	O
indicates	O
that	O
the	O
result	O
is	O
written	O
back	O
to	O
source	O
register	O
f	O
.	O
The	O
C	B-Language
and	O
Z	O
status	O
flags	O
may	O
be	O
set	O
based	O
on	O
the	O
result	O
;	O
otherwise	O
they	O
are	O
unmodified	O
.	O
</s>
<s>
Add	O
and	O
subtract	O
(	O
but	O
not	O
rotate	O
)	O
instructions	O
that	O
set	O
C	B-Language
also	O
set	O
the	O
DC	O
(	O
digit	O
carry	O
)	O
flag	O
,	O
the	O
carry	O
from	O
bit	O
3	O
to	O
bit	O
4	O
,	O
which	O
is	O
useful	O
for	O
BCD	O
arithmetic	O
.	O
</s>
<s>
Except	O
for	O
a	O
single	O
accumulator	O
(	O
called	O
W	O
)	O
,	O
almost	O
all	O
other	O
registers	O
are	O
memory-mapped	O
,	O
even	O
registers	O
like	O
the	O
program	B-General_Concept
counter	I-General_Concept
and	O
ALU	O
status	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
(	O
The	O
other	O
exceptions	O
,	O
which	O
are	O
not	O
memory-mapped	O
,	O
are	O
the	O
return	O
address	O
stack	O
,	O
and	O
the	O
tri-state	B-Device
registers	O
used	O
to	O
configure	O
the	O
GPIO	B-Architecture
pins	O
.	O
)	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
does	O
not	O
contain	O
conditional	O
branch	O
instructions	O
.	O
</s>
<s>
The	O
ALU	O
status	B-General_Concept
register	I-General_Concept
is	O
one	O
possibility	O
.	O
</s>
<s>
Memory	O
operands	O
are	O
specified	O
by	O
absolute	O
address	O
;	O
the	O
location	O
is	O
fixed	O
at	O
compile	B-Application
time	I-Application
.	O
</s>
<s>
To	O
provide	O
indirect	B-Language
addressing	I-Language
,	O
a	O
pair	O
of	O
special	O
function	O
registers	O
are	O
provided	O
:	O
</s>
<s>
The	O
indirect	O
file	O
register	O
(	O
INDF	O
)	O
becomes	O
an	O
alias	B-Application
for	O
the	O
operand	O
pointed	O
to	O
by	O
the	O
FSR	O
.	O
</s>
<s>
This	O
mechanism	O
also	O
allows	O
up	O
to	O
256	O
bytes	O
of	O
memory	O
to	O
be	O
addressed	O
,	O
even	O
when	O
the	O
instruction	B-General_Concept
set	I-General_Concept
only	O
allows	O
5	O
-	O
or	O
7-bit	O
memory	O
operands	O
.	O
</s>
<s>
PIC	B-Architecture
processors	O
with	O
more	O
than	O
256	O
words	O
of	O
program	O
use	O
paged	O
memory	O
.	O
</s>
<s>
The	O
internal	O
program	B-General_Concept
counter	I-General_Concept
and	O
return	O
stack	O
are	O
as	O
wide	O
as	O
necessary	O
to	O
address	O
all	O
memory	O
,	O
but	O
only	O
the	O
low	O
8	O
bits	O
are	O
visible	O
to	O
software	O
in	O
the	O
PCL	O
(	O
"	O
PC	O
low	O
"	O
)	O
register	O
.	O
</s>
<s>
+	O
12-bit	O
PIC	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
C	B-Language
?	O
</s>
<s>
Description	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
opcode	O
Miscellaneous	O
instructions	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
NOP	O
No	O
operation	O
(	O
MOVW	O
0	O
,	O
W	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
OPTION	O
Copy	O
W	O
to	O
OPTION	O
register	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
SLEEP	O
Go	O
into	O
standby	O
mode	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
CLRWDT	O
Restart	O
watchdog	O
timer	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
f	O
TRIS	O
f	O
Copy	O
W	O
to	O
tri-state	B-Device
register	O
(	O
f	O
=	O
1	O
,	O
2	O
or	O
3	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
k	O
MOVLB	O
k*	O
Set	O
bank	O
select	O
register	O
to	O
k	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
1	O
1	O
0	O
RETURN†	O
Return	O
from	O
subroutine	O
,	O
W	O
unmodified	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
1	O
1	O
1	O
RETFIE†	O
Return	O
from	O
interrupt	O
;	O
return	O
&	O
enable	O
interrupts	O
0	O
0	O
opcode	O
d	O
register	O
ALU	O
operations	O
:	O
dest	O
←	O
OP(f,W )	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
f	O
MOVWF	O
f	O
f	O
←	O
W	O
0	O
0	O
0	O
0	O
0	O
1	O
d	O
f	O
CLR	O
f	O
,	O
d	O
Z	O
dest	O
←	O
0	O
,	O
usually	O
written	O
CLRW	O
or	O
CLRF	O
f	O
0	O
0	O
0	O
0	O
1	O
0	O
d	O
f	O
SUBWF	O
f	O
,	O
d	O
C	B-Language
Z	O
dest	O
←	O
f−W	O
(	O
dest	O
←	O
f+	O
~	O
W+1	O
)	O
0	O
0	O
0	O
0	O
1	O
1	O
d	O
f	O
DECF	O
f	O
,	O
d	O
Z	O
dest	O
←	O
f−1	O
0	O
0	O
0	O
1	O
0	O
0	O
d	O
f	O
IORWF	O
f	O
,	O
d	O
Z	O
dest	O
←	O
f	O
W	O
,	O
logical	O
inclusive	O
or	O
0	O
0	O
0	O
1	O
0	O
1	O
d	O
f	O
ANDWF	O
f	O
,	O
d	O
Z	O
dest	O
←	O
f	O
&	O
W	O
,	O
logical	O
and	O
0	O
0	O
0	O
1	O
1	O
0	O
d	O
f	O
XORWF	O
f	O
,	O
d	O
Z	O
dest	O
←	O
f	O
^	O
W	O
,	O
logical	O
exclusive	O
or	O
0	O
0	O
0	O
1	O
1	O
1	O
d	O
f	O
ADDWF	O
f	O
,	O
d	O
C	B-Language
Z	O
dest	O
←	O
f+W	O
0	O
0	O
1	O
0	O
0	O
0	O
d	O
f	O
MOVF	O
f	O
,	O
d	O
Z	O
dest	O
←	O
f	O
0	O
0	O
1	O
0	O
0	O
1	O
d	O
f	O
COMF	O
f	O
,	O
d	O
Z	O
dest	O
←	O
~	O
f	O
,	O
bitwise	O
complement	O
0	O
0	O
1	O
0	O
1	O
0	O
d	O
f	O
INCF	O
f	O
,	O
d	O
Z	O
dest	O
←	O
f+1	O
0	O
0	O
1	O
0	O
1	O
1	O
d	O
f	O
DECFSZ	O
f	O
,	O
d	O
dest	O
←	O
f−1	O
,	O
then	O
skip	O
if	O
zero	O
0	O
0	O
1	O
1	O
0	O
0	O
d	O
f	O
RRF	O
f	O
,	O
d	O
C	B-Language
dest	O
←	O
CARRYxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1>4	O
,	O
swap	O
nibbles	O
0	O
0	O
1	O
1	O
1	O
1	O
d	O
f	O
INCFSZ	O
f	O
,	O
d	O
dest	O
←	O
f+1	O
,	O
then	O
skip	O
if	O
zero	O
0	O
1	O
opc	O
bit	O
register	O
Bit	O
operations	O
0	O
1	O
0	O
0	O
bit	O
f	O
BCF	O
f	O
,	O
b	O
Clear	O
bit	O
b	O
of	O
f	O
0	O
1	O
0	O
1	O
bit	O
f	O
BSF	O
f	O
,	O
b	O
Set	O
bit	O
b	O
of	O
f	O
0	O
1	O
1	O
0	O
bit	O
f	O
BTFSC	O
f	O
,	O
b	O
Skip	O
if	O
bit	O
b	O
of	O
f	O
is	O
clear	O
0	O
1	O
1	O
1	O
bit	O
f	O
BTFSS	O
f	O
,	O
b	O
Skip	O
if	O
bit	O
b	O
of	O
f	O
is	O
set	O
1	O
0	O
opc	O
k	O
Control	O
transfers	O
1	O
0	O
0	O
0	O
k	O
RETLW	O
k	O
Set	O
W	O
←	O
k	O
,	O
then	O
return	O
from	O
subroutine	O
1	O
0	O
0	O
1	O
k	O
CALL	O
k	O
Call	O
subroutine	O
,	O
8-bit	O
address	O
k	O
1	O
0	O
1	O
k	O
GOTO	O
k	O
Jump	O
to	O
9-bit	O
address	O
k	O
1	O
1	O
opc	O
8-bit	O
immediate	O
Operations	O
with	O
W	O
and	O
8-bit	O
literal	O
:	O
W	O
←	O
OP(k,W )	O
1	O
1	O
0	O
0	O
k	O
MOVLW	O
k	O
W	O
←	O
k	O
1	O
1	O
0	O
1	O
k	O
IORLW	O
k	O
Z	O
W	O
←	O
k	O
W	O
,	O
bitwise	O
logical	O
or	O
1	O
1	O
1	O
0	O
k	O
ANDLW	O
k	O
Z	O
W	O
←	O
k	O
&	O
W	O
,	O
bitwise	O
and	O
1	O
1	O
1	O
1	O
k	O
XORLW	O
k	O
Z	O
W	O
←	O
k	O
^	O
W	O
,	O
bitwise	O
exclusive	O
or	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
C	B-Language
?	O
</s>
<s>
ELAN	O
Microelectronics	O
Corp	O
.	O
make	O
a	O
series	O
of	O
PICmicro-like	O
microcontrollers	B-Architecture
with	O
a	O
13-bit	O
instruction	O
word	O
.	O
</s>
<s>
The	O
instructions	O
are	O
mostly	O
compatible	O
with	O
the	O
mid-range	O
14-bit	O
instruction	B-General_Concept
set	I-General_Concept
,	O
but	O
limited	O
to	O
a	O
6-bit	O
register	O
address	O
(	O
16	O
special-purpose	O
registers	O
and	O
48	O
bytes	O
of	O
RAM	O
)	O
and	O
a	O
10-bit	O
(	O
1024	O
word	O
)	O
program	O
space	O
.	O
</s>
<s>
The	O
10-bit	O
program	B-General_Concept
counter	I-General_Concept
is	O
accessible	O
as	O
R2	O
.	O
</s>
<s>
The	O
7	O
accumulator-immediate	O
instructions	O
are	O
renumbered	O
relative	O
to	O
the	O
14-bit	O
PICmicro	B-Architecture
,	O
to	O
fit	O
into	O
3	O
opcode	O
bits	O
rather	O
than	O
4	O
,	O
but	O
they	O
are	O
all	O
there	O
,	O
as	O
well	O
as	O
an	O
additional	O
software	O
interrupt	O
instruction	O
.	O
</s>
<s>
There	O
are	O
a	O
few	O
additional	O
miscellaneous	O
instructions	O
,	O
and	O
there	O
are	O
some	O
changes	O
to	O
the	O
terminology	O
(	O
the	O
PICmicro	B-Architecture
OPTION	O
register	O
is	O
called	O
the	O
CONTrol	O
register	O
;	O
the	O
PICmicro	B-Architecture
TRIS	O
registers	O
1	O
–	O
3	O
are	O
called	O
I/O	O
control	O
registers	O
5	O
–	O
7	O
)	O
,	O
but	O
the	O
equivalents	O
are	O
obvious	O
.	O
</s>
<s>
+	O
13-bit	O
EM78	O
instruction	B-General_Concept
set	I-General_Concept
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
C	B-Language
?	O
</s>
<s>
Description	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
opcode	O
Miscellaneous	O
instructions	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
NOP*	O
No	O
operation	O
(	O
MOVW	O
0	O
,	O
W	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
DAA†	O
C	B-Language
Decimal	O
Adjust	O
after	O
Addition	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
CONTW*	O
Write	O
CONT	O
register	O
(	O
CONT	O
←	O
W	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
SLEP*	O
Go	O
into	O
standby	O
mode	O
(	O
WDT	O
←	O
0	O
,	O
stop	O
clock	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
WDTC*	O
Restart	O
watchdog	O
timer	O
(	O
WDT	O
←	O
0	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
f	O
IOW	O
f	O
Copy	O
W	O
to	O
I/O	O
control	O
register	O
(	O
f	O
=	O
5	O
–	O
7	O
,	O
11	O
–	O
15	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
0	O
0	O
ENI†	O
Enable	O
interrupts	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
0	O
1	O
DISI†	O
Disable	O
interrupts	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
1	O
0	O
RET	O
Return	O
from	O
subroutine	O
,	O
W	O
unmodified	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
1	O
1	O
RETI	O
Return	O
from	O
interrupt	O
;	O
return	O
&	O
enable	O
interrupts	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
1	O
0	O
0	O
CONTR†	O
Read	O
CONT	O
register	O
(	O
W	O
←	O
CONT	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
f	O
IOR	O
f	O
Copy	O
I/O	O
control	O
register	O
to	O
W	O
(	O
f	O
=	O
5	O
–	O
7	O
,	O
11	O
–	O
15	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
0	O
0	O
0	O
TBL†	O
C	B-Language
Z	O
PCL	O
+	O
=	O
W	O
,	O
preserve	O
PC	O
bits	O
8	O
&	O
9	O
0	O
0	O
opcode	O
d	O
register	O
ALU	O
operations	O
same	O
as	O
12	O
-	O
and	O
14-bit	O
PIC	B-Architecture
0	O
1	O
opc	O
bit	O
register	O
Bit	O
operations	O
same	O
as	O
12	O
-	O
and	O
14-bit	O
PIC	B-Architecture
1	O
0	O
c	B-Language
k	O
Control	O
transfers	O
same	O
as	O
14-bit	O
PIC	B-Architecture
1	O
1	O
opcode	O
8-bit	O
immediate	O
Operations	O
with	O
W	O
and	O
8-bit	O
literal	O
:	O
W	O
←	O
OP(k,W )	O
1	O
1	O
0	O
op	O
k	O
MOV/IOR/AND/XOR	O
,	O
same	O
as	O
12-bit	O
PIC	B-Architecture
1	O
1	O
1	O
0	O
0	O
k	O
RETLW	O
k	O
W	O
←	O
k	O
,	O
then	O
return	O
from	O
subroutine	O
1	O
1	O
1	O
0	O
1	O
k	O
SUBLW	O
k	O
C	B-Language
Z	O
W	O
←	O
k−W	O
(	O
W	O
←	O
k+	O
~	O
W+1	O
)	O
1	O
1	O
1	O
1	O
0	O
0	O
k	O
INT	O
k†	O
Push	O
PC	O
,	O
PC	O
←	O
k	O
(	O
software	O
interrupt	O
,	O
usually	O
k	O
=	O
1	O
)	O
1	O
1	O
1	O
1	O
1	O
k	O
ADDLW	O
k	O
C	B-Language
Z	O
W	O
←	O
k+W	O
1	O
1	O
1	O
1	O
0	O
1	O
opcode	O
k	O
Extensions	O
(	O
replacing	O
INT	O
k	O
for	O
k≥128	O
on	O
later	O
models	O
)	O
1	O
1	O
1	O
1	O
0	O
1	O
0	O
0	O
0	O
k	O
PAGE	O
k	O
Select	O
ROM	O
page	O
k	O
(	O
like	O
MOVLP	O
k	O
)	O
1	O
1	O
1	O
1	O
0	O
1	O
0	O
0	O
1	O
k	O
BANK	O
k†	O
Select	O
RAM	O
bank	O
k	O
1	O
1	O
1	O
1	O
0	O
1	O
0	O
1	O
0	O
k	O
LCALL	O
k†	O
Long	O
call	O
with	O
17-bit	O
address	O
(	O
2-word	O
instruction	O
)	O
1	O
1	O
1	O
1	O
0	O
1	O
0	O
1	O
1	O
k	O
LJMP	O
k†	O
Long	O
jump	O
with	O
17-bit	O
address	O
(	O
2-word	O
instruction	O
)	O
1	O
1	O
1	O
1	O
0	O
1	O
1	O
f	O
TBRD	O
f	O
Read	O
ROM	O
at	O
TBHP:TBLP	O
into	O
specified	O
register	O
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
C	B-Language
?	O
</s>
<s>
Some	O
models	O
support	O
multiple	O
ROM	O
or	O
RAM	O
banks	O
,	O
in	O
a	O
manner	O
similar	O
to	O
other	O
PIC	B-Architecture
microcontrollers	I-Architecture
.	O
</s>
<s>
There	O
is	O
also	O
a	O
15-bit	O
variant	O
of	O
the	O
instruction	B-General_Concept
set	I-General_Concept
,	O
which	O
is	O
almost	O
identical	O
except	O
that	O
the	O
register	O
numbers	O
are	O
enlarged	O
to	O
8	O
bits	O
and	O
the	O
call	O
and	O
jump	O
addresses	O
are	O
enlarged	O
to	O
12	O
bits	O
.	O
</s>
<s>
A	O
second	O
generation	O
15-bit	O
instruction	B-General_Concept
set	I-General_Concept
includes	O
several	O
additional	O
instructions	O
:	O
</s>
<s>
+	O
15-bit	O
EM78/EM88	O
instruction	B-General_Concept
set	I-General_Concept
extensionsDerived	O
from	O
instruction	O
encoding	O
tables	O
in	O
Elan	O
eUIDE	O
II	O
v2.19.60.14	O
,	O
released	O
2019-05-01	O
,	O
accessed	O
2019-07-13	O
.	O
</s>
<s>
14	O
13	O
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
C	B-Language
?	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
differs	O
very	O
little	O
from	O
the	O
baseline	O
devices	O
,	O
but	O
the	O
2	O
additional	O
opcode	O
bits	O
allow	O
128	O
registers	O
and	O
2048	O
words	O
of	O
code	O
to	O
be	O
directly	O
addressed	O
.	O
</s>
<s>
The	O
mid-range	O
core	O
is	O
available	O
in	O
the	O
majority	O
of	O
devices	O
labeled	O
PIC12	B-Architecture
and	O
PIC16	B-Architecture
.	O
</s>
<s>
+	O
14-bit	O
PIC	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
13	O
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
C	B-Language
?	O
</s>
<s>
Description	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
opcode	O
Miscellaneous	O
instructions	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
NOP	O
No	O
operation	O
(	O
MOVW	O
0	O
,	O
W	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
0	O
RETURN	O
Return	O
from	O
subroutine	O
,	O
W	O
unmodified	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
1	O
RETFIE	O
Return	O
from	O
interrupt	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
0	O
0	O
0	O
1	O
0	O
OPTION	O
Copy	O
W	O
to	O
OPTION	O
register	O
(	O
deprecated	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
0	O
0	O
0	O
1	O
1	O
SLEEP	O
Go	O
into	O
standby	O
mode	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
0	O
0	O
1	O
0	O
0	O
CLRWDT	O
Restart	O
watchdog	O
timer	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
0	O
0	O
1	O
f	O
TRIS	O
f	O
Copy	O
W	O
to	O
tri-state	B-Device
register	O
(	O
f	O
=	O
1	O
,	O
2	O
or	O
3	O
)	O
(	O
deprecated	O
)	O
0	O
0	O
opcode	O
d	O
register	O
ALU	O
operations	O
:	O
dest	O
←	O
OP(f,W )	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
f	O
MOVWF	O
f	O
f	O
←	O
W	O
0	O
0	O
0	O
0	O
0	O
1	O
d	O
f	O
CLR	O
f	O
,	O
d	O
Z	O
dest	O
←	O
0	O
,	O
usually	O
written	O
CLRW	O
or	O
CLRF	O
f	O
0	O
0	O
0	O
0	O
1	O
0	O
d	O
f	O
SUBWF	O
f	O
,	O
d	O
C	B-Language
Z	O
dest	O
←	O
f−W	O
(	O
dest	O
←	O
f+	O
~	O
W+1	O
)	O
0	O
0	O
0	O
0	O
1	O
1	O
d	O
f	O
DECF	O
f	O
,	O
d	O
Z	O
dest	O
←	O
f−1	O
0	O
0	O
0	O
1	O
0	O
0	O
d	O
f	O
IORWF	O
f	O
,	O
d	O
Z	O
dest	O
←	O
f	O
W	O
,	O
logical	O
inclusive	O
or	O
0	O
0	O
0	O
1	O
0	O
1	O
d	O
f	O
ANDWF	O
f	O
,	O
d	O
Z	O
dest	O
←	O
f	O
&	O
W	O
,	O
logical	O
and	O
0	O
0	O
0	O
1	O
1	O
0	O
d	O
f	O
XORWF	O
f	O
,	O
d	O
Z	O
dest	O
←	O
f	O
^	O
W	O
,	O
logical	O
exclusive	O
or	O
0	O
0	O
0	O
1	O
1	O
1	O
d	O
f	O
ADDWF	O
f	O
,	O
d	O
C	B-Language
Z	O
dest	O
←	O
f+W	O
0	O
0	O
1	O
0	O
0	O
0	O
d	O
f	O
MOVF	O
f	O
,	O
d	O
Z	O
dest	O
←	O
f	O
0	O
0	O
1	O
0	O
0	O
1	O
d	O
f	O
COMF	O
f	O
,	O
d	O
Z	O
dest	O
←	O
~	O
f	O
,	O
bitwise	O
complement	O
0	O
0	O
1	O
0	O
1	O
0	O
d	O
f	O
INCF	O
f	O
,	O
d	O
Z	O
dest	O
←	O
f+1	O
0	O
0	O
1	O
0	O
1	O
1	O
d	O
f	O
DECFSZ	O
f	O
,	O
d	O
dest	O
←	O
f−1	O
,	O
then	O
skip	O
if	O
zero	O
0	O
0	O
1	O
1	O
0	O
0	O
d	O
f	O
RRF	O
f	O
,	O
d	O
C	B-Language
dest	O
←	O
CARRYxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1>4	O
,	O
swap	O
nibbles	O
0	O
0	O
1	O
1	O
1	O
1	O
d	O
f	O
INCFSZ	O
f	O
,	O
d	O
dest	O
←	O
f+1	O
,	O
then	O
skip	O
if	O
zero	O
0	O
1	O
opc	O
bit	O
register	O
Bit	O
operations	O
0	O
1	O
0	O
0	O
bit	O
f	O
BCF	O
f	O
,	O
b	O
Clear	O
bit	O
b	O
of	O
f	O
0	O
1	O
0	O
1	O
bit	O
f	O
BSF	O
f	O
,	O
b	O
Set	O
bit	O
b	O
of	O
f	O
0	O
1	O
1	O
0	O
bit	O
f	O
BTFSC	O
f	O
,	O
b	O
Skip	O
if	O
bit	O
b	O
of	O
f	O
is	O
clear	O
0	O
1	O
1	O
1	O
bit	O
f	O
BTFSS	O
f	O
,	O
b	O
Skip	O
if	O
bit	O
b	O
of	O
f	O
is	O
set	O
1	O
0	O
c	B-Language
k	O
Control	O
transfers	O
1	O
0	O
0	O
k	O
CALL	O
k	O
Call	O
subroutine	O
1	O
0	O
1	O
k	O
GOTO	O
k	O
Jump	O
to	O
address	O
k	O
1	O
1	O
opcode	O
8-bit	O
immediate	O
Operations	O
with	O
W	O
and	O
8-bit	O
literal	O
:	O
W	O
←	O
OP(k,W )	O
1	O
1	O
0	O
0	O
x	O
x	O
k	O
MOVLW	O
k	O
W	O
←	O
k	O
1	O
1	O
0	O
1	O
x	O
x	O
k	O
RETLW	O
k	O
W	O
←	O
k	O
,	O
then	O
return	O
from	O
subroutine	O
1	O
1	O
1	O
0	O
0	O
0	O
k	O
IORLW	O
k	O
Z	O
W	O
←	O
k	O
W	O
,	O
bitwise	O
logical	O
or	O
1	O
1	O
1	O
0	O
0	O
1	O
k	O
ANDLW	O
k	O
Z	O
W	O
←	O
k	O
&	O
W	O
,	O
bitwise	O
and	O
1	O
1	O
1	O
0	O
1	O
0	O
k	O
XORLW	O
k	O
Z	O
W	O
←	O
k	O
^	O
W	O
,	O
bitwise	O
exclusive	O
or	O
1	O
1	O
1	O
0	O
1	O
1	O
k	O
(	O
reserved	O
)	O
1	O
1	O
1	O
1	O
0	O
x	O
k	O
SUBLW	O
k	O
C	B-Language
Z	O
W	O
←	O
k−W	O
(	O
dest	O
←	O
k+	O
~	O
W+1	O
)	O
1	O
1	O
1	O
1	O
1	O
x	O
k	O
ADDLW	O
k	O
C	B-Language
Z	O
W	O
←	O
k+W	O
13	O
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
C	B-Language
?	O
</s>
<s>
Enhanced	O
mid-range	O
core	O
devices	O
introduce	O
a	O
deeper	O
hardware	O
stack	O
,	O
additional	O
reset	O
methods	O
,	O
14	O
additional	O
instructions	O
and	O
C	B-Language
programming	I-Language
language	I-Language
optimizations	O
.	O
</s>
<s>
Special	O
instructions	O
use	O
FSRn	O
registers	O
like	O
address	O
registers	O
,	O
with	O
a	O
variety	O
of	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
+	O
14-bit	O
enhanced	O
PIC	B-Architecture
additional	O
instructions	O
13	O
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
C	B-Language
?	O
</s>
<s>
Description	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
opcode	O
Miscellaneous	O
instructions	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
RESET	O
Software	O
reset	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
1	O
0	O
CALLW	O
Push	O
PC	O
,	O
then	O
jump	O
to	O
PCLATH:W	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
1	O
1	O
BRW	O
PC	O
←	O
PC	O
+	O
W	O
,	O
relative	O
jump	O
using	O
W	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
n	O
0	O
0	O
MOVIW	O
++FSRn	O
Z	O
Increment	O
FSRn	O
,	O
then	O
W	O
←	O
INDFn	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
n	O
0	O
1	O
MOVIW	O
−−FSRn	O
Z	O
Decrement	O
FSRn	O
,	O
then	O
W	O
←	O
INDFn	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
n	O
1	O
0	O
MOVIW	O
FSRn++	O
Z	O
W	O
←	O
INDFn	O
,	O
then	O
increment	O
FSRn	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
n	O
1	O
1	O
MOVIW	O
FSRn−−	O
Z	O
W	O
←	O
INDFn	O
,	O
then	O
decrement	O
FSRn	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
n	O
m	O
MOVWI	O
using	O
FSRn	O
INDFn	O
←	O
W	O
,	O
same	O
modes	O
as	O
MOVIW	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
k	O
MOVLB	O
k	O
BSR	O
←	O
k	O
,	O
move	O
literal	O
to	O
bank	O
select	O
register	O
1	O
1	O
opcode	O
d	O
register	O
ALU	O
operations	O
:	O
dest	O
←	O
OP(f,W )	O
1	O
1	O
0	O
1	O
0	O
1	O
d	O
f	O
LSLF	O
f	O
,	O
d	O
C	B-Language
Z	O
dest	O
←	O
f	O
<< 1, logical shift left 1  1  0  1  1  0  d  f  LSRF f,d  C  Z  dest ← f >> 1, logical shift right 1  1  0  1  1  1  d  f  ASRF f,d  C  Z  dest ← f >>	O
1	O
,	O
arithmetic	O
shift	O
right	O
1	O
1	O
1	O
0	O
1	O
1	O
d	O
f	O
SUBWFB	O
f	O
,	O
d	O
C	B-Language
Z	O
dest	O
←	O
f	O
+	O
~	O
W	O
+	O
C	B-Language
,	O
subtract	O
with	O
carry	O
1	O
1	O
1	O
1	O
0	O
1	O
d	O
f	O
ADDWFC	O
f	O
,	O
d	O
C	B-Language
Z	O
dest	O
←	O
f	O
+	O
W	O
+	O
C	B-Language
,	O
add	O
with	O
carry	O
1	O
1	O
opcode	O
k	O
Operations	O
with	O
literal	O
k	O
1	O
1	O
0	O
0	O
0	O
1	O
0	O
n	O
k	O
ADDFSR	O
FSRn	O
,	O
k	O
FSRn	O
←	O
FSRn	O
+	O
k	O
,	O
add	O
6-bit	O
signed	O
offset	O
1	O
1	O
0	O
0	O
0	O
1	O
1	O
k	O
MOVLP	O
k	O
PCLATH	O
←	O
k	O
,	O
move	O
7-bit	O
literal	O
to	O
PC	O
latch	O
high	O
1	O
1	O
0	O
0	O
1	O
k	O
BRA	O
k	O
PC	O
←	O
PC	O
+	O
k	O
,	O
branch	O
relative	O
using	O
9-bit	O
signed	O
offset	O
1	O
1	O
1	O
1	O
1	O
1	O
0	O
n	O
k	O
MOVIW	O
k[FSRn]	O
Z	O
W	O
←	O
[FSRn+k],	O
6-bit	O
signed	O
offset	O
1	O
1	O
1	O
1	O
1	O
1	O
1	O
n	O
k	O
MOVWI	O
k[FSRn]	O
 [ FSRn+k ] 	O
←	O
W	O
,	O
6-bit	O
signed	O
offset	O
13	O
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
C	B-Language
?	O
</s>
<s>
Holtek	O
make	O
numerous	O
8-bit	O
microcontrollers	B-Architecture
with	O
a	O
14-bit	O
instruction	O
word	O
equivalent	O
to	O
the	O
(	O
non-enhanced	O
)	O
mid-range	O
core	O
.	O
</s>
<s>
Several	O
operations	O
have	O
been	O
added	O
to	O
the	O
14-bit	O
PICmicro	B-Architecture
repertoire	O
:	O
</s>
<s>
Holtek	O
provide	O
two	O
indirect	B-Language
addressing	I-Language
registers	O
,	O
like	O
the	O
enhanced	O
14-bit	O
PIC	B-Architecture
.	O
</s>
<s>
+	O
14-bit	O
Holtek	O
instruction	B-General_Concept
set	I-General_Concept
13	O
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
PIC	B-Architecture
equiv	O
.	O
</s>
<s>
C	B-Language
?	O
</s>
<s>
Read	O
from	O
last	O
page	O
of	O
ROM	O
at	O
0xff:TBLP	O
0	O
1	O
1	O
1	O
1	O
0	O
0	O
m	O
(	O
reserved	O
)	O
0	O
1	O
1	O
1	O
1	O
0	O
1	O
m	O
DAA	O
 [ m ] 	O
—	O
C	B-Language
 [ m ] 	O
←	O
DAA(ACC )	O
,	O
decimal	O
adjust	O
after	O
BCD	O
addition	O
0	O
1	O
1	O
1	O
1	O
1	O
0	O
m	O
CLR	O
 [ m ] 	O
≈CLRF	O
m	O
 [ m ] 	O
←	O
0	O
0	O
1	O
1	O
1	O
1	O
1	O
1	O
m	O
SET	O
 [ m ] 	O
—	O
 [ m ] 	O
←	O
255	O
1	O
0	O
c	B-Language
k	O
Control	O
transfers	O
1	O
0	O
0	O
k	O
CALL	O
k	O
CALL	O
k	O
Call	O
subroutine	O
1	O
0	O
1	O
k	O
JMP	O
k	O
GOTO	O
k	O
Jump	O
to	O
address	O
k	O
1	O
1	O
opc	O
bit	O
address	O
Bit	O
operations	O
1	O
1	O
0	O
0	O
bit	O
m	O
SET	O
[m].b	O
BSF	O
m	O
,	O
b	O
Set	O
bit	O
b	O
of	O
 [ m ] 	O
1	O
1	O
0	O
1	O
bit	O
m	O
CLR	O
[m].b	O
BCF	O
m	O
,	O
b	O
Clear	O
bit	O
b	O
of	O
 [ m ] 	O
1	O
1	O
1	O
0	O
bit	O
m	O
SNZ	O
[m].b	O
BTFSS	O
m	O
,	O
b	O
Skip	O
if	O
bit	O
b	O
of	O
 [ m ] 	O
is	O
set	O
1	O
1	O
1	O
1	O
bit	O
m	O
SZ	O
[m].b	O
BTFSC	O
m	O
,	O
b	O
Skip	O
if	O
bit	O
b	O
of	O
 [ m ] 	O
is	O
clear	O
13	O
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
PIC	B-Architecture
equiv	O
.	O
</s>
<s>
C	B-Language
?	O
</s>
<s>
Padauk	O
Technology	O
make	O
a	O
series	O
of	O
PIC-like	O
microcontrollers	B-Architecture
notable	O
for	O
their	O
extremely	O
low	O
cost	O
,	O
beginning	O
at	O
in	O
quantity	O
,	O
with	O
many	O
models	O
costing	O
less	O
than	O
.	O
</s>
<s>
Although	O
clearly	O
derived	O
from	O
the	O
Microchip	O
PIC12	B-Architecture
series	O
,	O
</s>
<s>
They	O
do	O
not	O
use	O
the	O
FSR/INDF	O
mechanism	O
for	O
performing	O
indirect	O
memory	O
access	O
,	O
instead	O
having	O
indirect	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
which	O
use	O
an	O
arbitrary	O
RAM	O
location	O
as	O
a	O
pointer	O
;	O
</s>
<s>
the	O
carry	B-Algorithm
flag	I-Algorithm
uses	O
a	O
"	O
borrow	O
bit	O
"	O
convention	O
for	O
subtracts	O
,	O
rather	O
than	O
the	O
"	O
carry	B-Algorithm
bit	I-Algorithm
"	O
convention	O
used	O
by	O
Microchip	O
;	O
</s>
<s>
they	O
also	O
include	O
a	O
signed	O
overflow	B-Algorithm
flag	I-Algorithm
,	O
which	O
like	O
the	O
digit	O
carry	O
,	O
is	O
set	O
by	O
add	O
,	O
subtract	O
and	O
compare	O
instructions	O
(	O
every	O
instruction	O
which	O
sets	O
the	O
carry	B-Algorithm
flag	I-Algorithm
except	O
for	O
shift	O
instructions	O
)	O
;	O
</s>
<s>
they	O
have	O
separate	O
RAM	O
and	O
I/O	O
register	O
addresses	O
spaces	O
(	O
64	O
and	O
32	O
bytes	O
,	O
respectively	O
,	O
in	O
the	O
13-bit	O
instruction	B-General_Concept
set	I-General_Concept
)	O
;	O
</s>
<s>
some	O
models	O
support	O
temporal	B-Operating_System
multithreading	I-Operating_System
,	O
having	O
multiple	O
execution	O
contexts	O
whose	O
execution	O
is	O
interleaved	O
.	O
</s>
<s>
+	O
13-bit	O
Padauk	O
instruction	B-General_Concept
set	I-General_Concept
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
PICequivalent	O
C	B-Language
?	O
</s>
<s>
Description	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
opcode	O
Miscellaneous	O
instructions	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
NOP	O
NOP	O
No	O
operation	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
(	O
reserved	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
x	O
(	O
reserved	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
x	O
(	O
reserved	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
0	O
LDSPTL	O
—	O
A	O
←	O
ROM[[SP]],	O
load	O
low/high	O
byte	O
of	O
ROM	O
word	O
using	O
16-bit	O
pointer	O
on	O
top	O
of	O
stack	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
1	O
LDSPTH	O
—	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
—	O
(	O
reserved	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
opcode	O
One-operand	O
instructions	O
on	O
accumulatorSame	O
as	O
one-operand	O
instructions	O
on	O
memory	O
(	O
below	O
)	O
except	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
1	O
1	O
1	O
PCADD	O
A	O
≈ADDWF	O
PCL	O
,	O
1	O
PC	O
←	O
PC	O
+	O
A	O
,	O
add	O
to	O
program	B-General_Concept
counter	I-General_Concept
(	O
not	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
1	O
1	O
0	O
SWAP	O
A	O
—	O
A	O
←	O
Axxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1	O
1	O
,	O
rotate	O
right	O
through	O
carry	O
0	O
1	O
0	O
1	O
1	O
0	O
1	O
address	O
SLC	O
addr	O
RLF	O
addr	O
,	O
1	O
C	B-Language
 [ addr ] 	O
←	O
 [ addr ] 	O
<<	O
1	O
C	B-Language
,	O
rotate	O
left	O
through	O
carry	O
0	O
1	O
0	O
1	O
1	O
1	O
0	O
address	O
CEQSN	O
addr	O
—	O
C	B-Language
Z	O
Compute	O
A	O
−	O
[addr],	O
then	O
skip	O
if	O
zero	O
0	O
1	O
0	O
1	O
1	O
1	O
1	O
address	O
(	O
reserved	O
for	O
CNEQSN	O
)	O
0	O
1	O
1	O
opc	O
bit	O
address	O
Bit	O
operations	O
with	O
I/O	O
0	O
1	O
1	O
0	O
0	O
bit	O
address	O
T0SN	O
ioaddr.b	O
BTFSC	O
ioaddr	O
,	O
b	O
Skip	O
if	O
bit	O
b	O
of	O
 [ ioaddr ] 	O
is	O
clear	O
0	O
1	O
1	O
0	O
1	O
bit	O
address	O
T1SN	O
ioaddr.b	O
BTFSS	O
ioaddr	O
,	O
b	O
Skip	O
if	O
bit	O
b	O
of	O
 [ ioaddr ] 	O
is	O
set	O
0	O
1	O
1	O
1	O
0	O
bit	O
address	O
SET0	O
ioaddr.b	O
BCF	O
ioaddr	O
,	O
b	O
Clear	O
bit	O
b	O
of	O
 [ ioaddr ] 	O
0	O
1	O
1	O
1	O
1	O
bit	O
address	O
SET1	O
ioaddr.b	O
BSF	O
ioaddr	O
,	O
b	O
Set	O
bit	O
b	O
of	O
 [ ioaddr ] 	O
1	O
0	O
opcode	O
literal	O
Literal	O
operations	O
:	O
A	O
←	O
OP(A,k )	O
1	O
0	O
0	O
0	O
0	O
k	O
ADD	O
A	O
,	O
k	O
ADDLW	O
k	O
C	B-Language
Z	O
A	O
←	O
A	O
+	O
k	O
1	O
0	O
0	O
0	O
1	O
k	O
SUB	O
A	O
,	O
k	O
≠SUBLW	O
k	O
C	B-Language
Z	O
A	O
←	O
A	O
−	O
k	O
1	O
0	O
0	O
1	O
0	O
k	O
CEQSN	O
A	O
,	O
k	O
—	O
C	B-Language
Z	O
Compute	O
A	O
−	O
k	O
,	O
then	O
skip	O
if	O
zero	O
1	O
0	O
0	O
1	O
1	O
k	O
(	O
reserved	O
for	O
CNEQSN	O
)	O
1	O
0	O
1	O
0	O
0	O
k	O
AND	O
A	O
,	O
k	O
≈ANDLW	O
k	O
Z	O
A	O
←	O
A	O
&	O
k	O
1	O
0	O
1	O
0	O
1	O
k	O
OR	O
A	O
,	O
k	O
≈IORLW	O
k	O
Z	O
A	O
←	O
A	O
k	O
1	O
0	O
1	O
1	O
0	O
k	O
XOR	O
A	O
,	O
k	O
≈XORLW	O
k	O
Z	O
A	O
←	O
A	O
^	O
k	O
1	O
0	O
1	O
1	O
1	O
k	O
MOV	O
A	O
,	O
k	O
MOVLW	O
k	O
A	O
←	O
k	O
1	O
1	O
c	B-Language
k	O
Control	O
transfers	O
:	O
PC	O
←	O
k	O
1	O
1	O
0	O
k	O
GOTO	O
k	O
GOTO	O
k	O
PC	O
←	O
k	O
1	O
1	O
1	O
k	O
CALL	O
k	O
CALL	O
k	O
Push	O
PC	O
,	O
then	O
PC	O
←	O
k	O
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
PICequivalent	O
C	B-Language
?	O
</s>
<s>
The	O
14-	O
,	O
15	O
-	O
and	O
16-bit	O
instruction	B-General_Concept
sets	I-General_Concept
primarily	O
differ	O
in	O
having	O
wider	O
address	O
fields	O
,	O
although	O
some	O
encoding	O
changes	O
are	O
made	O
to	O
allow	O
a	O
few	O
additional	O
instructions	O
(	O
such	O
as	O
,	O
which	O
performs	O
a	O
compare	O
and	O
skip	O
if	O
not	O
equal	O
.	O
)	O
</s>
<s>
+	O
14-bit	O
Padauk	O
instruction	B-General_Concept
set	I-General_Concept
13	O
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
PICequivalent	O
C	B-Language
?	O
</s>
<s>
Description	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
opcode	O
Miscellaneous	O
instructions	O
same	O
as	O
13-bit	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
—	O
(	O
reserved	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
—	O
(	O
reserved	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
—	O
(	O
reserved	O
)	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
0	O
opcode	O
One-operand	O
instructions	O
on	O
A	O
same	O
as	O
13-bit	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
1	O
opcode	O
System	O
control	O
instructions	O
same	O
as	O
13-bit	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
—	O
(	O
reserved	O
)	O
0	O
0	O
0	O
0	O
0	O
opcode	O
address	O
Byte-wide	O
I/O	O
operations	O
same	O
as	O
13-bit	O
,	O
but	O
opcodes	O
changed	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
ioaddr	O
XOR	O
ioaddr	O
,	O
A	O
—	O
IO[ioaddr]	O
←	O
A	O
^	O
IO[address]	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
—	O
(	O
reserved	O
)	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
0	O
ioaddr	O
MOV	O
ioaddr	O
,	O
A	O
—	O
IO[ioaddr]	O
←	O
A	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
1	O
ioaddr	O
MOV	O
A	O
,	O
ioaddr	O
—	O
Z	O
A	O
←	O
IO[ioaddr]	O
0	O
0	O
0	O
0	O
1	O
0	O
k	O
Return	O
literal	O
constant	O
same	O
as	O
13-bit	O
0	O
0	O
0	O
0	O
1	O
1	O
c	B-Language
address	O
c	B-Language
16-bit	O
operations	O
same	O
as	O
13-bit	O
,	O
but	O
128-byte	O
range	O
0	O
0	O
0	O
1	O
0	O
bit	O
address	O
Copy	O
bit	O
to	O
I/O	O
0	O
0	O
0	O
1	O
0	O
bit	O
address	O
SWAPC	O
ioaddr.b	O
—	O
C	B-Language
Swap	O
carry	O
with	O
 [ ioaddr ] 	O
bit	O
b	O
0	O
0	O
0	O
1	O
1	O
c	B-Language
d	O
address	O
Additional	O
2-operand	O
operations	O
0	O
0	O
0	O
1	O
1	O
0	O
0	O
address	O
COMP	O
A	O
,	O
addr	O
—	O
C	B-Language
Z	O
A	O
−	O
[addr],	O
flags	O
set	O
,	O
result	O
discarded	O
0	O
0	O
0	O
1	O
1	O
0	O
1	O
address	O
COMP	O
addr	O
,	O
A	O
—	O
C	B-Language
Z	O
 [ addr ] 	O
−	O
A	O
,	O
flags	O
set	O
,	O
result	O
discarded	O
0	O
0	O
0	O
1	O
1	O
1	O
0	O
address	O
NADD	O
A	O
,	O
addr	O
SUBWF	O
addr	O
,	O
0	O
C	B-Language
Z	O
A	O
←	O
 [ addr ] 	O
+	O
−A	O
(	O
A	O
←	O
 [ addr ] 	O
+	O
~	O
A	O
+	O
1	O
)	O
0	O
0	O
0	O
1	O
1	O
1	O
1	O
address	O
NADD	O
addr	O
,	O
A	O
—	O
C	B-Language
Z	O
 [ addr ] 	O
←	O
A	O
+	O
−[addr]	O
( [	O
addr ]	O
←	O
A	O
+	O
~[addr]	O
+	O
1	O
)	O
0	O
0	O
1	O
d	O
opcode	O
address	O
2-operand	O
instructions	O
same	O
as	O
13-bit	O
0	O
1	O
0	O
opcode	O
address	O
One-operand	O
operations	O
on	O
memory	O
same	O
as	O
13-bit	O
,	O
plus	O
CNEQSN	O
0	O
1	O
0	O
1	O
1	O
1	O
1	O
address	O
CNEQSN	O
addr	O
—	O
C	B-Language
Z	O
Compute	O
A	O
−	O
[addr],	O
then	O
skip	O
if	O
non-zero	O
0	O
1	O
1	O
opc	O
bit	O
ioaddr	O
Bit	O
operations	O
with	O
I/O	O
same	O
as	O
13-bit	O
,	O
but	O
64-byte	O
range	O
1	O
0	O
0	O
opc	O
bit	O
address	O
Bit	O
operations	O
with	O
memory	O
same	O
as	O
13-bit	O
,	O
but	O
64-byte	O
range	O
1	O
0	O
1	O
opcode	O
literal	O
Literal	O
operations	O
same	O
as	O
13-bit	O
,	O
plus	O
CNEQSN	O
1	O
0	O
1	O
0	O
1	O
1	O
k	O
CNEQSN	O
A	O
,	O
k	O
—	O
C	B-Language
Z	O
Compute	O
A	O
−	O
k	O
,	O
then	O
skip	O
if	O
non-zero	O
1	O
1	O
c	B-Language
k	O
Control	O
transfers	O
same	O
as	O
13-bit	O
113	O
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
PICequivalent	O
C	B-Language
?	O
</s>
<s>
In	O
contrast	O
to	O
earlier	O
devices	O
,	O
which	O
were	O
more	O
often	O
than	O
not	O
programmed	O
in	O
assembly	O
,	O
C	B-Language
has	O
become	O
the	O
predominant	O
development	O
language	O
.	O
</s>
<s>
The	O
PIC18	O
extends	O
the	O
FSR/INDF	O
mechanism	O
used	O
in	O
previous	O
PICmicro	B-Architecture
processors	O
for	O
indirect	B-Language
addressing	I-Language
in	O
two	O
ways	O
:	O
</s>
<s>
The	O
FSRn	O
registers	O
are	O
12	O
bits	O
long	O
(	O
each	O
split	O
into	O
two	O
8-bit	O
portions	O
FSR0L	O
through	O
FSR2H	O
)	O
,	O
and	O
access	O
to	O
the	O
corresponding	O
INDFn	O
register	O
(	O
INDF0	O
through	O
INDF2	O
)	O
acts	O
as	O
an	O
alias	B-Application
for	O
the	O
addressed	O
byte	O
.	O
</s>
<s>
Second	O
,	O
there	O
are	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
For	O
each	O
of	O
the	O
three	O
,	O
there	O
is	O
not	O
just	O
one	O
INDFn	O
register	O
,	O
but	O
five	O
,	O
and	O
the	O
one	O
used	O
determines	O
the	O
addressing	B-Language
mode	I-Language
:	O
</s>
<s>
PLUSWn	O
:	O
Access	O
the	O
byte	O
at	O
FSRn	O
+	O
W	O
(	O
indexed	B-Language
addressing	I-Language
)	O
.	O
</s>
<s>
+	O
PIC18	O
16-bit	O
instruction	B-General_Concept
set	I-General_Concept
15	O
14	O
13	O
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
C	B-Language
?	O
</s>
<s>
Description	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
opcode	O
Miscellaneous	O
instructions	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
NOP	O
No	O
operation	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
SLEEP	O
Go	O
into	O
standby	O
mode	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
CLRWDT	O
Restart	O
watchdog	O
timer	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
1	O
PUSH	O
Push	O
PC	O
on	O
top	O
of	O
stack	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
0	O
POP	O
Pop	O
(	O
and	O
discard	O
)	O
top	O
of	O
stack	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
1	O
DAW	O
C	B-Language
Decimal	O
adjust	O
W	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
0	O
TBLRD∗	O
Table	O
read	O
:	O
TABLAT	O
←	O
mem[TBLPTR]	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
1	O
TBLRD∗+	O
Table	O
read	O
with	O
postincrement	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
1	O
0	O
TBLRD∗−	O
Table	O
read	O
with	O
postdecrement	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
1	O
1	O
TBLRD+∗	O
Table	O
read	O
with	O
pre-increment	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
mod	O
TBLWR	O
Table	O
write	O
,	O
same	O
modes	O
as	O
TBLRD	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
0	O
s	O
RETFIE	O
[	O
,	O
FAST ]	O
Return	O
from	O
interrupt	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
1	O
s	O
RETURN	O
[	O
,	O
FAST ]	O
Return	O
from	O
subroutine	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
0	O
1	O
0	O
0	O
CALLW*	O
Push	O
PC	O
,	O
jump	O
to	O
PCLATU:PCLATH:W	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
1	O
1	O
1	O
1	O
1	O
1	O
1	O
RESET	O
0	O
0	O
0	O
Software	O
reset	O
0	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
—	O
0	O
—	O
k	O
MOVLB	O
Move	O
literal	O
k	O
to	O
bank	O
select	O
register	O
0	O
0	O
0	O
0	O
1	O
opcode	O
literal	O
Literal	O
operations	O
:	O
W	O
←	O
OP(k,W )	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
0	O
k	O
SUBLW	O
k	O
W	O
←	O
k	O
−	O
W	O
0	O
0	O
0	O
0	O
1	O
0	O
0	O
1	O
k	O
IORLW	O
k	O
W	O
←	O
k	O
W	O
,	O
logical	O
inclusive	O
or	O
0	O
0	O
0	O
0	O
1	O
0	O
1	O
0	O
k	O
XORLW	O
k	O
W	O
←	O
k	O
^	O
W	O
,	O
exclusive	O
or	O
0	O
0	O
0	O
0	O
1	O
0	O
1	O
1	O
k	O
ANDLW	O
k	O
W	O
←	O
k	O
&	O
W	O
,	O
logical	O
and	O
0	O
0	O
0	O
0	O
1	O
1	O
0	O
0	O
k	O
RETLW	O
k	O
RETURN	O
W	O
←	O
k	O
0	O
0	O
0	O
0	O
1	O
1	O
0	O
1	O
k	O
MULLW	O
k	O
W	O
←	O
k	O
×	O
W	O
0	O
0	O
0	O
0	O
1	O
1	O
1	O
0	O
k	O
MOVLW	O
k	O
W	O
←	O
k	O
0	O
0	O
0	O
0	O
1	O
1	O
1	O
1	O
k	O
ADDLW	O
k	O
W	O
←	O
k	O
+	O
W	O
0	O
opcode	O
d	O
a	O
register	O
ALU	O
operations	O
:	O
dest	O
←	O
OP(f,W )	O
0	O
0	O
0	O
0	O
0	O
0	O
1	O
a	O
f	O
MULWF	O
f	O
,	O
a	O
PRODH:PRODL	O
←	O
W	O
×	O
f	O
(	O
unsigned	O
)	O
0	O
0	O
0	O
0	O
0	O
1	O
d	O
a	O
f	O
DECF	O
f	O
,	O
d	O
,	O
a	O
C	B-Language
Z	O
N	O
dest	O
←	O
f	O
−	O
1	O
0	O
0	O
0	O
1	O
0	O
0	O
d	O
a	O
f	O
IORWF	O
f	O
,	O
d	O
,	O
a	O
Z	O
N	O
dest	O
←	O
f	O
W	O
,	O
logical	O
inclusive	O
or	O
0	O
0	O
0	O
1	O
0	O
1	O
d	O
a	O
f	O
ANDWF	O
f	O
,	O
d	O
,	O
a	O
Z	O
N	O
dest	O
←	O
f	O
&	O
W	O
,	O
logical	O
and	O
0	O
0	O
0	O
1	O
1	O
0	O
d	O
a	O
f	O
XORWF	O
f	O
,	O
d	O
,	O
a	O
Z	O
N	O
dest	O
←	O
f	O
^	O
W	O
,	O
exclusive	O
or	O
0	O
0	O
0	O
1	O
1	O
1	O
d	O
a	O
f	O
COMF	O
f	O
,	O
d	O
,	O
a	O
Z	O
N	O
dest	O
←	O
~	O
f	O
,	O
bitwise	O
complement	O
0	O
0	O
1	O
0	O
0	O
0	O
d	O
a	O
f	O
ADDWFC	O
f	O
,	O
d	O
,	O
a	O
C	B-Language
Z	O
N	O
dest	O
←	O
f	O
+	O
W	O
+	O
C	B-Language
0	O
0	O
1	O
0	O
0	O
1	O
d	O
a	O
f	O
ADDWF	O
f	O
,	O
d	O
,	O
a	O
C	B-Language
Z	O
N	O
dest	O
←	O
f	O
+	O
W	O
0	O
0	O
1	O
0	O
1	O
0	O
d	O
a	O
f	O
INCF	O
f	O
,	O
d	O
,	O
a	O
C	B-Language
Z	O
N	O
dest	O
←	O
f	O
+	O
1	O
0	O
0	O
1	O
0	O
1	O
1	O
d	O
a	O
f	O
DECFSZ	O
f	O
,	O
d	O
,	O
a	O
dest	O
←	O
f	O
−	O
1	O
,	O
skip	O
if	O
0	O
0	O
0	O
1	O
1	O
0	O
0	O
d	O
a	O
f	O
RRCF	O
f	O
,	O
d	O
,	O
a	O
C	B-Language
Z	O
N	O
dest	O
←	O
f>>1	O
Cxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1	O
W	O
(	O
unsigned	O
)	O
0	O
1	O
1	O
0	O
0	O
1	O
1	O
a	O
f	O
TSTFSZ	O
f	O
,	O
a	O
skip	O
if	O
f	O
==	O
0	O
0	O
1	O
1	O
0	O
1	O
0	O
0	O
a	O
f	O
SETF	O
f	O
,	O
a	O
f	O
←	O
0xFF	O
0	O
1	O
1	O
0	O
1	O
0	O
1	O
a	O
f	O
CLRF	O
f	O
,	O
a	O
1	O
f	O
←	O
0	O
,	O
PSR.Z	O
←	O
1	O
0	O
1	O
1	O
0	O
1	O
1	O
0	O
a	O
f	O
NEGF	O
f	O
,	O
a	O
C	B-Language
Z	O
N	O
f	O
←	O
−f	O
0	O
1	O
1	O
0	O
1	O
1	O
1	O
a	O
f	O
MOVWF	O
f	O
,	O
a	O
f	O
←	O
W	O
0	O
1	O
1	O
1	O
bit	O
a	O
f	O
BTG	O
f	O
,	O
b	O
,	O
a	O
Toggle	O
bit	O
b	O
of	O
f	O
1	O
0	O
opc	O
bit	O
a	O
register	O
Bit	O
operations	O
1	O
0	O
0	O
0	O
bit	O
a	O
f	O
BSF	O
f	O
,	O
b	O
,	O
a	O
Set	O
bit	O
b	O
of	O
f	O
1	O
0	O
0	O
1	O
bit	O
a	O
f	O
BCF	O
f	O
,	O
b	O
,	O
a	O
Clear	O
bit	O
b	O
of	O
f	O
1	O
0	O
1	O
0	O
bit	O
a	O
f	O
BTFSS	O
f	O
,	O
b	O
,	O
a	O
Skip	O
if	O
bit	O
b	O
of	O
f	O
is	O
set	O
1	O
0	O
1	O
1	O
bit	O
a	O
f	O
BTFSC	O
f	O
,	O
b	O
,	O
a	O
Skip	O
if	O
bit	O
b	O
of	O
f	O
is	O
clear	O
1	O
1	O
0	O
opc	O
address	O
Large-address	O
operations	O
1	O
1	O
0	O
0	O
source	O
MOVFF	O
s	O
,	O
d	O
Move	O
absolute	O
1	O
1	O
1	O
1	O
destination	O
1	O
1	O
0	O
1	O
0	O
n	O
BRA	O
n	O
Branch	O
to	O
PC	O
+	O
2n	O
1	O
1	O
0	O
1	O
1	O
n	O
RCALL	O
n	O
Subroutine	O
call	O
to	O
PC	O
+	O
2n	O
1	O
1	O
1	O
0	O
0	O
cond	O
n	O
Conditional	O
branch	O
(	O
to	O
PC+2n	O
)	O
1	O
1	O
1	O
0	O
0	O
0	O
0	O
0	O
n	O
BZ	O
n	O
Branch	O
if	O
PSR.Z	O
is	O
set	O
1	O
1	O
1	O
0	O
0	O
0	O
0	O
1	O
n	O
BNZ	O
n	O
Branch	O
if	O
PSR.Z	O
is	O
clear	O
1	O
1	O
1	O
0	O
0	O
0	O
1	O
0	O
n	O
BC	O
n	O
Branch	O
if	O
PSR.C	O
is	O
set	O
1	O
1	O
1	O
0	O
0	O
0	O
1	O
1	O
n	O
BNC	O
n	O
Branch	O
if	O
PSR.C	O
is	O
clear	O
1	O
1	O
1	O
0	O
0	O
1	O
0	O
0	O
n	O
BOV	O
n	O
Branch	O
if	O
PSR.V	O
is	O
set	O
1	O
1	O
1	O
0	O
0	O
1	O
0	O
1	O
n	O
BNOV	O
n	O
Branch	O
if	O
PSR.V	O
is	O
clear	O
1	O
1	O
1	O
0	O
0	O
1	O
1	O
0	O
n	O
BN	O
n	O
Branch	O
if	O
PSR.N	O
is	O
set	O
1	O
1	O
1	O
0	O
0	O
1	O
1	O
1	O
n	O
BNN	O
n	O
Branch	O
if	O
PSR.N	O
is	O
clear	O
1	O
1	O
1	O
0	O
1	O
0	O
opc	O
k	O
Extensions	O
for	O
using	O
FSR2	O
as	O
software	O
stack	O
pointer*	O
1	O
1	O
1	O
0	O
1	O
0	O
0	O
0	O
n	O
k	O
ADDFSR	O
n	O
,	O
k*	O
FSRn	O
+	O
=	O
k	O
1	O
1	O
1	O
0	O
1	O
0	O
0	O
0	O
1	O
1	O
k	O
ADDULNK	O
k*	O
FSR2	O
+	O
=	O
k	O
,	O
pop	O
PC	O
1	O
1	O
1	O
0	O
1	O
0	O
0	O
1	O
n	O
k	O
SUBFSR	O
n	O
,	O
k*	O
FSRn	O
−	O
=	O
k	O
1	O
1	O
1	O
0	O
1	O
0	O
0	O
1	O
1	O
1	O
k	O
SUBULNK	O
k*	O
FSR2	O
−	O
=	O
k	O
,	O
pop	O
PC	O
1	O
1	O
1	O
0	O
1	O
0	O
1	O
0	O
k	O
PUSHL	O
k*	O
 [ FSR2 ] 	O
←	O
k	O
,	O
decrement	O
FSR2	O
1	O
1	O
1	O
0	O
1	O
0	O
1	O
1	O
0	O
s	O
MOVSF	O
src	O
,	O
f*	O
f	O
←	O
FSR2[s]	O
1	O
1	O
1	O
1	O
f	O
1	O
1	O
1	O
0	O
1	O
0	O
1	O
1	O
1	O
s	O
MOVSS	O
src	O
,	O
dst*	O
FSR2[d]	O
←	O
FSR2[s]	O
1	O
1	O
1	O
1	O
—	O
0	O
—	O
d	O
1	O
1	O
1	O
0	O
1	O
1	O
opc	O
k	O
2-word	O
instructions	O
1	O
1	O
1	O
0	O
1	O
1	O
0	O
s	O
k	O
(	O
lsbits	O
)	O
CALL	O
k[ 	O
,	O
FAST ]	O
Call	O
subroutine	O
(	O
20-bit	O
address	O
)	O
1	O
1	O
1	O
1	O
k	O
(	O
msbits	O
)	O
1	O
1	O
1	O
0	O
1	O
1	O
1	O
0	O
0	O
0	O
f	O
k	O
(	O
msb	O
)	O
LFSR	O
f	O
,	O
k	O
Move	O
12-bit	O
literal	O
to	O
FSRf	O
1	O
1	O
1	O
1	O
0	O
0	O
0	O
0	O
k	O
(	O
lsbits	O
)	O
1	O
1	O
1	O
0	O
1	O
1	O
1	O
1	O
k	O
(	O
lsbits	O
)	O
GOTO	O
k	O
Absolute	O
jump	O
,	O
PC	O
←	O
k	O
(	O
20-bit	O
address	O
)	O
1	O
1	O
1	O
1	O
k	O
(	O
msbits	O
)	O
1	O
1	O
1	O
1	O
k	O
No	O
operation	O
,	O
second	O
word	O
of	O
2-word	O
instructions	O
15	O
14	O
13	O
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
C	B-Language
?	O
</s>
<s>
They	O
are	O
Microchip	O
's	O
first	O
inherently	O
16-bit	O
microcontrollers	B-Architecture
.	O
</s>
<s>
PIC24	O
devices	O
are	O
designed	O
as	O
general	O
purpose	O
microcontrollers	B-Architecture
.	O
</s>
<s>
dsPIC	O
devices	O
include	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
capabilities	O
in	O
addition	O
.	O
</s>
<s>
One	O
is	O
like	O
the	O
classic	O
one-operand	O
PIC	B-Architecture
instructions	O
,	O
with	O
an	O
operation	O
between	O
W0	O
and	O
a	O
value	O
in	O
a	O
specified	O
f	O
register	O
(	O
i.e.	O
</s>
<s>
The	O
other	O
form	O
,	O
new	O
to	O
the	O
PIC24	O
,	O
specifies	O
three	O
W	O
register	O
operands	O
,	O
two	O
of	O
which	O
allow	O
a	O
3-bit	O
addressing	B-Language
mode	I-Language
specification	O
:	O
</s>
<s>
The	O
register	O
offset	O
addressing	B-Language
mode	I-Language
is	O
only	O
available	O
for	O
the	O
MOV	O
src	O
,	O
dst	O
instruction	O
,	O
where	O
the	O
Ww	O
register	O
may	O
be	O
used	O
as	O
a	O
register	O
offset	O
for	O
the	O
source	O
,	O
destination	O
,	O
or	O
both	O
.	O
</s>
<s>
+	O
PIC24	O
24-bit	O
instruction	B-General_Concept
set	I-General_Concept
23	O
22	O
21	O
20	O
19	O
18	O
17	O
16	O
15	O
14	O
13	O
12	O
11	O
10	O
9	O
8	O
7	O
6	O
5	O
4	O
3	O
2	O
1	O
0	O
Mnemonic	O
C	B-Language
?	O
</s>
