<s>
The	O
PA-8000	B-General_Concept
(	O
PCX-U	O
)	O
,	O
code-named	O
Onyx	O
,	O
is	O
a	O
microprocessor	B-Architecture
developed	O
and	O
fabricated	O
by	O
Hewlett-Packard	O
(	O
HP	O
)	O
that	O
implemented	O
the	O
PA-RISC	B-Device
2.0	I-Device
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
.	O
</s>
<s>
It	O
was	O
a	O
completely	O
new	O
design	O
with	O
no	O
circuitry	O
derived	O
from	O
previous	O
PA-RISC	B-Device
microprocessors	B-Architecture
.	O
</s>
<s>
The	O
PA-8000	B-General_Concept
was	O
introduced	O
on	O
2	O
November	O
1995	O
when	O
shipments	O
began	O
to	O
members	O
of	O
the	O
Precision	O
RISC	O
Organization	O
(	O
PRO	O
)	O
.	O
</s>
<s>
All	O
follow-on	O
PA-8x00	O
processors	O
(	O
PA-8200	B-General_Concept
to	O
PA-8900	B-General_Concept
,	O
described	O
further	O
below	O
)	O
are	O
based	O
on	O
the	O
basic	O
PA-8000	B-General_Concept
processor	O
core	O
.	O
</s>
<s>
The	O
PA-8000	B-General_Concept
was	O
used	O
by	O
:	O
</s>
<s>
The	O
PA-8000	B-General_Concept
is	O
a	O
four-way	O
superscalar	B-General_Concept
microprocessor	B-Architecture
that	O
executes	O
instructions	O
out-of-order	B-General_Concept
and	O
speculatively	B-General_Concept
.	O
</s>
<s>
These	O
features	O
were	O
not	O
found	O
in	O
previous	O
PA-RISC	B-Device
implementations	O
,	O
making	O
the	O
PA-8000	B-General_Concept
the	O
first	O
PA-RISC	B-Device
CPU	O
to	O
break	O
the	O
tradition	O
of	O
using	O
simple	O
microarchitectures	O
and	O
high-clock	O
rate	O
implementation	O
to	O
attain	O
performance	O
.	O
</s>
<s>
The	O
PA-8000	B-General_Concept
has	O
a	O
four-stage	O
front-end	O
.	O
</s>
<s>
The	O
IFU	O
contains	O
the	O
program	B-General_Concept
counter	I-General_Concept
,	O
branch	O
history	O
table	O
(	O
BHT	O
)	O
,	O
branch	O
target	O
address	O
cache	O
(	O
BTAC	O
)	O
and	O
a	O
four-entry	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	O
)	O
.	O
</s>
<s>
The	O
PA-8000	B-General_Concept
performs	O
branch	B-General_Concept
prediction	I-General_Concept
using	O
static	O
or	O
dynamic	O
methods	O
.	O
</s>
<s>
Which	O
method	O
the	O
PA-8000	B-General_Concept
used	O
was	O
selected	O
by	O
a	O
bit	O
in	O
each	O
TLB	O
entry	O
.	O
</s>
<s>
Each	O
BHT	O
entry	O
is	O
a	O
three-bit	O
shift	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
The	O
PA-8000	B-General_Concept
used	O
a	O
majority	O
vote	O
algorithm	O
,	O
a	O
branch	O
is	O
taken	O
if	O
the	O
majority	O
of	O
the	O
three	O
bits	O
are	O
set	O
,	O
and	O
not	O
taken	O
if	O
they	O
are	O
clear	O
.	O
</s>
<s>
Although	O
the	O
PA-8000	B-General_Concept
can	O
execute	O
two	O
branch	O
instructions	O
per	O
cycle	O
,	O
only	O
one	O
of	O
the	O
outcomes	O
is	O
recorded	O
as	O
the	O
BHT	O
is	O
not	O
dual-ported	O
to	O
simplify	O
its	O
implementation	O
.	O
</s>
<s>
The	O
PA-8000	B-General_Concept
has	O
a	O
two-cycle	O
bubble	O
for	O
correctly	O
predicted	O
branches	O
,	O
as	O
the	O
target	O
address	O
of	O
the	O
branch	O
must	O
be	O
calculated	O
before	O
it	O
is	O
sent	O
to	O
the	O
instruction	O
cache	O
.	O
</s>
<s>
To	O
reduce	O
the	O
occurrence	O
of	O
this	O
bubble	O
,	O
the	O
PA-8000	B-General_Concept
uses	O
a	O
32-entry	O
fully	O
associative	O
BTAC	O
.	O
</s>
<s>
The	O
IRB	O
's	O
purpose	O
is	O
the	O
implement	O
register	B-Architecture
renaming	I-Architecture
,	O
out	B-General_Concept
of	I-General_Concept
order	I-General_Concept
execution	I-General_Concept
,	O
speculative	B-General_Concept
execution	I-General_Concept
and	O
to	O
provide	O
a	O
temporary	O
place	O
for	O
results	O
to	O
be	O
stored	O
until	O
the	O
instructions	O
are	O
retired	O
.	O
</s>
<s>
The	O
IRB	O
consists	O
of	O
two	O
buffers	O
,	O
one	O
for	O
integer	O
and	O
floating-point	O
instructions	O
,	O
the	O
other	O
for	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
.	O
</s>
<s>
Integer	O
instructions	O
except	O
for	O
multiply	O
are	O
executed	O
in	O
two	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
(	O
ALUs	O
)	O
and	O
two	O
shift/merge	O
units	O
.	O
</s>
<s>
Both	O
integer	O
and	O
floating-point	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
are	O
executed	O
by	O
two	O
dedicated	O
address	O
adders	O
.	O
</s>
<s>
The	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	O
)	O
contains	O
96	O
entries	O
and	O
is	O
dual-ported	O
and	O
full-associative	O
.	O
</s>
<s>
Each	O
TLB	O
entry	O
can	O
be	O
mapped	O
to	O
a	O
page	B-General_Concept
with	O
a	O
size	O
between	O
4KB	O
to	O
16MB	O
,	O
in	O
increments	O
that	O
are	O
powers	O
of	O
four	O
.	O
</s>
<s>
The	O
PA-8000	B-General_Concept
has	O
a	O
data	O
cache	O
with	O
a	O
capacity	O
up	O
to	O
4MB	O
.	O
</s>
<s>
The	O
external	O
interface	O
is	O
the	O
Runway	B-Architecture
bus	I-Architecture
,	O
a	O
64-bit	O
address	O
and	O
data	O
multiplexed	O
bus	O
.	O
</s>
<s>
The	O
PA-8000	B-General_Concept
uses	O
a	O
40-bit	O
physical	B-General_Concept
address	I-General_Concept
,	O
thus	O
it	O
is	O
able	O
to	O
address	O
1TB	O
of	O
physical	O
memory	O
.	O
</s>
<s>
The	O
PA-8000	B-General_Concept
has	O
3.8	O
million	O
transistors	O
and	O
measures	O
17.68mm	O
by	O
19.10mm	O
,	O
for	O
an	O
area	O
of	O
337.69mm2	O
.	O
</s>
<s>
It	O
is	O
packaged	O
in	O
a	O
1,085	O
-pad	O
flip	B-Device
chip	I-Device
alumina	O
ceramic	B-Algorithm
land	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
LGA	O
)	O
.	O
</s>
<s>
The	O
PA-8000	B-General_Concept
uses	O
a	O
3.3V	O
power	O
supply	O
.	O
</s>
<s>
The	O
PA-8200	B-General_Concept
(	O
PCX-U	O
+	O
)	O
,	O
code-named	O
Vulcan	O
,	O
was	O
a	O
further	O
development	O
of	O
the	O
PA-8000	B-General_Concept
.	O
</s>
<s>
The	O
first	O
systems	O
to	O
use	O
the	O
PA-8200	B-General_Concept
became	O
available	O
in	O
June	O
1997	O
.	O
</s>
<s>
The	O
PA-8200	B-General_Concept
operated	O
at	O
200	O
to	O
240MHz	O
and	O
primarily	O
competed	O
with	O
the	O
Alpha	B-General_Concept
21164	I-General_Concept
.	O
</s>
<s>
Improvements	O
were	O
made	O
to	O
branch	B-General_Concept
prediction	I-General_Concept
and	O
the	O
TLB	O
.	O
</s>
<s>
Branch	B-General_Concept
prediction	I-General_Concept
was	O
improved	O
by	O
quadrupling	O
the	O
number	O
of	O
BHT	O
entries	O
to	O
1	O
,	O
024	O
,	O
which	O
required	O
the	O
use	O
of	O
a	O
two-bit	O
algorithm	O
in	O
order	O
to	O
fit	O
without	O
redesign	O
of	O
surrounding	O
circuitry	O
;	O
and	O
by	O
implementing	O
a	O
write	O
queue	O
that	O
enabled	O
two	O
branch	O
outcomes	O
to	O
be	O
recorded	O
by	O
the	O
BHT	O
instead	O
of	O
one	O
.	O
</s>
<s>
The	O
PA-8200	B-General_Concept
'	O
s	O
die	O
was	O
identical	O
in	O
size	O
to	O
the	O
PA-8000	B-General_Concept
as	O
improvements	O
utilized	O
empty	O
areas	O
of	O
the	O
die	O
.	O
</s>
<s>
The	O
PA-8500	B-General_Concept
(	O
PCX-W	O
)	O
,	O
code-named	O
Barracuda	O
,	O
is	O
a	O
further	O
development	O
of	O
the	O
PA-8200	B-General_Concept
.	O
</s>
<s>
The	O
PA-8500	B-General_Concept
core	O
measured	O
10.8mm	O
by	O
11.4mm	O
(	O
123.12mm2	O
)	O
in	O
the	O
new	O
process	O
,	O
less	O
than	O
half	O
the	O
area	O
of	O
the	O
0.5μm	O
PA-8200	B-General_Concept
.	O
</s>
<s>
The	O
PA-8500	B-General_Concept
has	O
a	O
512KB	O
instruction	O
cache	O
and	O
a	O
1MB	O
data	O
cache	O
.	O
</s>
<s>
Other	O
improvements	O
to	O
the	O
microarchitecture	O
include	O
a	O
larger	O
BHT	O
containing	O
2,048	O
entries	O
,	O
twice	O
the	O
capacity	O
of	O
the	O
PA-8200	B-General_Concept
'	O
s	O
,	O
and	O
a	O
larger	O
TLB	O
containing	O
160	O
entries	O
.	O
</s>
<s>
The	O
PA-8500	B-General_Concept
uses	O
a	O
new	O
version	O
of	O
the	O
Runway	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
As	O
the	O
Runway	B-Architecture
bus	I-Architecture
is	O
used	O
to	O
transfer	O
addresses	O
and	O
data	O
,	O
usable	O
bandwidth	O
is	O
80%	O
that	O
of	O
2GB/s	O
,	O
or	O
around	O
1.6GB/s	O
.	O
</s>
<s>
The	O
PA-8500	B-General_Concept
contains	O
140	O
million	O
transistors	O
and	O
measures	O
21.3mm	O
by	O
22.0mm	O
(	O
468.6mm2	O
)	O
.	O
</s>
<s>
HP	O
did	O
not	O
fabricate	O
the	O
PA-8500	B-General_Concept
themselves	O
as	O
they	O
had	O
ceased	O
to	O
upgrade	O
their	O
fabs	O
to	O
implement	O
a	O
process	O
newer	O
than	O
CMOS-14C	O
,	O
which	O
was	O
used	O
to	O
fabricate	O
previous	O
PA-RISC	B-Device
microprocessors	B-Architecture
.	O
</s>
<s>
The	O
PA-8500	B-General_Concept
was	O
packaged	O
in	O
a	O
smaller	O
544-pad	O
land	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
LGA	O
)	O
as	O
the	O
integration	O
of	O
the	O
primary	O
caches	O
on	O
die	O
resulted	O
in	O
the	O
removal	O
of	O
the	O
two	O
128-bit	O
buses	O
which	O
communicated	O
with	O
the	O
external	O
caches	O
and	O
their	O
associated	O
I/O	O
pads	O
.	O
</s>
<s>
The	O
PA-8600	B-General_Concept
(	O
PCX-W	O
+	O
)	O
,	O
code-named	O
Landshark	O
,	O
is	O
a	O
further	O
development	O
of	O
the	O
PA-8500	B-General_Concept
introduced	O
in	O
January	O
2000	O
.	O
</s>
<s>
The	O
PA-8600	B-General_Concept
was	O
intended	O
to	O
be	O
introduced	O
in	O
mid-2000	O
.	O
</s>
<s>
It	O
was	O
a	O
tweaked	O
version	O
of	O
the	O
PA-8500	B-General_Concept
to	O
enable	O
it	O
to	O
reach	O
higher	O
clock	O
frequencies	O
of	O
480	O
to	O
550MHz	O
.	O
</s>
<s>
The	O
PA-8700	B-General_Concept
(	O
PCX-W2	O
)	O
,	O
code-named	O
Piranha	O
,	O
is	O
a	O
further	O
development	O
of	O
the	O
PA-8600	B-General_Concept
.	O
</s>
<s>
Improvements	O
were	O
the	O
implementation	O
of	O
data	O
prefetching	O
,	O
a	O
quasi-LRU	O
replacement	O
policy	O
for	O
the	O
data	O
cache	O
,	O
and	O
a	O
larger	O
44-bit	O
physical	B-General_Concept
address	I-General_Concept
space	O
to	O
address	O
16TB	O
of	O
physical	O
memory	O
.	O
</s>
<s>
The	O
PA-8700	B-General_Concept
also	O
has	O
larger	O
instruction	O
and	O
data	O
caches	O
,	O
increased	O
in	O
capacity	O
by	O
50%	O
to	O
0.75MB	O
and	O
1.5MB	O
,	O
respectively	O
.	O
</s>
<s>
The	O
PA-8700	B-General_Concept
was	O
fabricated	O
by	O
IBM	O
Microelectronics	O
in	O
a	O
0.18μm	O
silicon	B-Algorithm
on	I-Algorithm
insulator	I-Algorithm
(	O
SOI	O
)	O
CMOS	O
process	O
with	O
seven	O
levels	O
of	O
copper	O
interconnect	O
and	O
low-κ	B-Algorithm
dielectric	I-Algorithm
.	O
</s>
<s>
The	O
PA-8700	B-General_Concept
+	I-General_Concept
was	O
a	O
further	O
development	O
of	O
the	O
PA-8700	B-General_Concept
introduced	O
in	O
systems	O
in	O
mid-2002	O
.	O
</s>
<s>
The	O
PA-8800	B-General_Concept
,	O
code-named	O
Mako	O
,	O
is	O
a	O
further	O
development	O
of	O
the	O
PA-8700	B-General_Concept
.	O
</s>
<s>
It	O
was	O
introduced	O
in	O
2004	O
and	O
was	O
used	O
by	O
HP	O
in	O
their	O
C8000	B-Device
workstation	O
and	O
HP	B-Device
9000	I-Device
Superdome	I-Device
servers	O
.	O
</s>
<s>
The	O
PA-8800	B-General_Concept
was	O
a	O
dual-core	B-Architecture
design	O
consisting	O
of	O
two	O
modified	O
PA-8700	B-General_Concept
+	I-General_Concept
microprocessors	B-Architecture
on	O
a	O
single	O
die	O
.	O
</s>
<s>
The	O
primary	O
caches	O
are	O
smaller	O
than	O
those	O
in	O
the	O
PA-8700	B-General_Concept
to	O
enable	O
both	O
cores	O
to	O
fit	O
on	O
the	O
same	O
die	O
.	O
</s>
<s>
Improvements	O
over	O
the	O
PA-8700	B-General_Concept
are	O
improved	O
branch	B-General_Concept
prediction	I-General_Concept
and	O
the	O
inclusion	O
of	O
an	O
external	O
32MB	O
unified	O
secondary	O
cache	O
.	O
</s>
<s>
The	O
PA-8800	B-General_Concept
used	O
the	O
same	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
as	O
the	O
McKinley	O
Itanium	B-General_Concept
microprocessor	I-General_Concept
,	O
which	O
yields	O
6.4GB/s	O
of	O
bandwidth	O
,	O
and	O
is	O
compatible	O
with	O
HP	O
's	O
Itanium	B-General_Concept
chipsets	O
such	O
as	O
the	O
zx1	B-General_Concept
.	O
</s>
<s>
It	O
was	O
fabricated	O
by	O
IBM	O
in	O
0.13μm	O
SOI	O
process	O
with	O
copper	O
interconnects	O
and	O
low-κ	B-Algorithm
dielectric	I-Algorithm
.	O
</s>
<s>
The	O
PA-8800	B-General_Concept
is	O
packaged	O
in	O
a	O
ceramic	O
ball	O
grid	O
array	O
mounted	O
on	O
a	O
printed	O
circuit	O
board	O
(	O
PCB	O
)	O
with	O
the	O
four	O
ESRAMs	O
,	O
forming	O
a	O
module	O
similar	O
to	O
those	O
used	O
by	O
early	O
Itanium	B-General_Concept
microprocessors	I-General_Concept
.	O
</s>
<s>
The	O
PA-8900	B-General_Concept
,	O
code-named	O
Shortfin	O
,	O
was	O
a	O
derivative	O
of	O
the	O
PA-8800	B-General_Concept
.	O
</s>
<s>
It	O
was	O
the	O
last	O
PA-RISC	B-Device
microprocessor	B-Architecture
to	O
be	O
developed	O
and	O
was	O
introduced	O
on	O
31	O
May	O
2005	O
when	O
systems	O
using	O
the	O
microprocessor	B-Architecture
became	O
available	O
.	O
</s>
<s>
It	O
was	O
used	O
in	O
the	O
HP	B-Device
9000	I-Device
servers	O
and	O
the	O
C8000	B-Device
workstation	O
.	O
</s>
<s>
It	O
is	O
not	O
a	O
die	O
shrink	O
of	O
the	O
PA-8800	B-General_Concept
,	O
as	O
was	O
earlier	O
rumored	O
.	O
</s>
<s>
It	O
uses	O
the	O
McKinley	O
system	O
bus	O
and	O
was	O
compatible	O
with	O
Itanium	B-General_Concept
2	O
chipsets	O
such	O
as	O
the	O
HP	O
zx1	B-General_Concept
.	O
</s>
