<s>
The	O
PA-7100LC	O
is	O
a	O
microprocessor	B-Architecture
that	O
implements	O
the	O
PA-RISC	B-Device
1.1	I-Device
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
developed	O
by	O
Hewlett-Packard	O
(	O
HP	O
)	O
.	O
</s>
<s>
It	O
was	O
designed	O
as	O
a	O
low-cost	O
microprocessor	B-Architecture
for	O
low-end	O
systems	O
.	O
</s>
<s>
The	O
PA-7100LC	O
was	O
the	O
first	O
PA-RISC	B-Device
microprocessor	B-Architecture
to	O
implement	O
the	O
MAX-1	B-General_Concept
multimedia	O
instructions	O
,	O
an	O
early	O
single	B-Device
instruction	I-Device
,	I-Device
multiple	I-Device
data	I-Device
(	O
SIMD	B-Device
)	O
multimedia	O
instruction	B-General_Concept
set	I-General_Concept
extension	O
that	O
provided	O
instructions	O
for	O
improving	O
the	O
performance	O
of	O
MPEG	O
video	O
decoding	O
.	O
</s>
<s>
The	O
PA-7100LC	O
was	O
based	O
on	O
the	O
PA-7100	B-General_Concept
.	O
</s>
<s>
Major	O
improvements	O
were	O
improved	O
superscalar	B-General_Concept
execution	I-General_Concept
and	O
an	O
extra	O
integer	O
unit	O
.	O
</s>
<s>
The	O
PA-7100LC	O
also	O
implemented	O
architectural	O
improvements	O
including	O
the	O
MAX-1	B-General_Concept
multimedia	O
instructions	O
,	O
uncacheable	O
memory	O
pages	O
,	O
and	O
bi-endian	O
support	O
.	O
</s>
<s>
Superscalar	B-General_Concept
execution	I-General_Concept
was	O
improved	O
by	O
adding	O
the	O
extra	O
integer	O
unit	O
and	O
modifying	O
the	O
control	O
logic	O
so	O
that	O
two	O
integer	O
instructions	O
,	O
two	O
load-store	B-Architecture
units	I-Architecture
,	O
or	O
an	O
integer	O
and	O
a	O
load-store	O
can	O
be	O
issued	O
in	O
one	O
cycle	O
in	O
addition	O
to	O
the	O
existing	O
instruction	O
combinations	O
supported	O
by	O
the	O
PA-7100	B-General_Concept
.	O
</s>
<s>
Prominently	O
,	O
the	O
floating-point	B-General_Concept
unit	I-General_Concept
multiplier	O
was	O
modified	O
to	O
take	O
up	O
less	O
area	O
by	O
halving	O
the	O
tree	O
of	O
carry-save	O
adders	O
that	O
summed	O
the	O
partial	O
products	O
of	O
the	O
mantissa	B-Algorithm
.	O
</s>
<s>
Integrated	O
on-die	O
to	O
lower	O
costs	O
is	O
a	O
memory	B-General_Concept
controller	I-General_Concept
that	O
supports	O
up	O
to	O
2GB	O
of	O
memory	O
and	O
an	O
I/O	O
controller	O
.	O
</s>
<s>
The	O
organization	O
of	O
the	O
caches	O
is	O
different	O
from	O
that	O
of	O
most	O
HP-designed	O
PA-RISC	B-Device
CPUs	O
.	O
</s>
<s>
The	O
PA-7100LC	O
is	O
packaged	O
in	O
a	O
432-pin	O
ceramic	B-Algorithm
pin	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
.	O
</s>
<s>
The	O
PA-7300LC	B-Device
was	O
a	O
further	O
development	O
of	O
the	O
PA-7100LC	O
.	O
</s>
<s>
It	O
was	O
introduced	O
in	O
mid-1996	O
as	O
a	O
low-end	O
to	O
mid-range	O
microprocessor	B-Architecture
complementing	O
the	O
high-end	O
PA-8000	B-General_Concept
in	O
HP	O
's	O
workstations	O
and	O
servers	O
.	O
</s>
<s>
The	O
PA-7300LC	B-Device
integrates	O
an	O
improved	O
PA-7100LC	O
,	O
64KB	O
instruction	O
and	O
data	O
caches	O
,	O
L2	O
cache	O
controller	O
,	O
memory	B-General_Concept
controller	I-General_Concept
and	O
a	O
GSC	B-Architecture
bus	I-Architecture
controller	O
onto	O
a	O
single	O
chip	O
.	O
</s>
<s>
It	O
was	O
the	O
first	O
PA-RISC	B-Device
microprocessor	B-Architecture
to	O
include	O
any	O
significant	O
amount	O
of	O
on-chip	O
cache	O
.	O
</s>
<s>
The	O
PA-7300LC	B-Device
contained	O
9.2	O
million	O
transistors	O
,	O
of	O
which	O
1.2	O
million	O
are	O
used	O
in	O
logic	O
and	O
8	O
million	O
are	O
used	O
in	O
the	O
caches	O
;	O
and	O
measured	O
15.3	O
by	O
17.0mm	O
for	O
an	O
area	O
of	O
260.1mm2	O
.	O
</s>
