<s>
The	O
P6	B-Device
microarchitecture	I-Device
is	O
the	O
sixth-generation	O
Intel	B-Operating_System
x86	I-Operating_System
microarchitecture	B-General_Concept
,	O
implemented	O
by	O
the	O
Pentium	B-Device
Pro	I-Device
microprocessor	O
that	O
was	O
introduced	O
in	O
November	O
1995	O
.	O
</s>
<s>
It	O
is	O
frequently	O
referred	O
to	O
as	O
i686	B-Device
.	O
</s>
<s>
It	O
was	O
planned	O
to	O
be	O
succeeded	O
by	O
the	O
NetBurst	B-Device
microarchitecture	B-General_Concept
used	O
by	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
in	O
2000	O
,	O
but	O
was	O
revived	O
for	O
the	O
Pentium	B-Architecture
M	I-Architecture
line	O
of	O
microprocessors	O
.	O
</s>
<s>
The	O
successor	O
to	O
the	O
Pentium	B-Architecture
M	I-Architecture
variant	O
of	O
the	O
P6	B-Device
microarchitecture	I-Device
is	O
the	O
Core	B-Device
microarchitecture	I-Device
which	O
in	O
turn	O
is	O
also	O
derived	O
from	O
P6	B-Device
.	O
</s>
<s>
P6	B-Device
was	O
used	O
within	O
Intel	O
's	O
mainstream	O
offerings	O
from	O
the	O
Pentium	B-Device
Pro	I-Device
to	O
Pentium	B-General_Concept
III	I-General_Concept
,	O
and	O
was	O
widely	O
known	O
for	O
low	O
power	O
consumption	O
,	O
excellent	O
integer	O
performance	O
,	O
and	O
relatively	O
high	O
instructions	B-Device
per	O
cycle	O
(	O
IPC	O
)	O
.	O
</s>
<s>
The	O
P6	B-Device
core	B-Device
was	O
the	O
sixth	O
generation	O
Intel	O
microprocessor	O
in	O
the	O
x86	B-Operating_System
line	O
.	O
</s>
<s>
The	O
first	O
implementation	O
of	O
the	O
P6	B-Device
core	B-Device
was	O
the	O
Pentium	B-Device
Pro	I-Device
CPU	O
in	O
1995	O
,	O
the	O
immediate	O
successor	O
to	O
the	O
original	B-General_Concept
Pentium	I-General_Concept
design	O
(	O
P5	B-General_Concept
)	O
.	O
</s>
<s>
P6	B-Device
processors	O
dynamically	O
translate	O
IA-32	B-Device
instructions	B-Device
into	O
sequences	O
of	O
buffered	O
RISC-like	O
micro-operations	B-General_Concept
,	O
then	O
analyze	O
and	O
reorder	O
the	O
micro-operations	B-General_Concept
to	O
detect	O
parallelizable	O
operations	O
that	O
may	O
be	O
issued	O
to	O
more	O
than	O
one	O
execution	B-General_Concept
unit	I-General_Concept
at	O
once	O
.	O
</s>
<s>
The	O
Pentium	B-Device
Pro	I-Device
was	O
the	O
first	O
x86	B-Operating_System
microprocessor	I-Operating_System
designed	O
by	O
Intel	O
to	O
use	O
this	O
technique	O
,	O
though	O
the	O
NexGen	O
Nx586	B-Device
,	O
introduced	O
in	O
1994	O
,	O
did	O
so	O
earlier	O
.	O
</s>
<s>
Other	O
features	O
first	O
implemented	O
in	O
the	O
x86	B-Operating_System
space	O
in	O
the	O
P6	B-Device
core	B-Device
include	O
:	O
</s>
<s>
Speculative	B-General_Concept
execution	I-General_Concept
and	O
out-of-order	B-General_Concept
completion	I-General_Concept
(	O
called	O
"	O
dynamic	B-General_Concept
execution	I-General_Concept
"	O
by	O
Intel	O
)	O
,	O
which	O
required	O
new	O
retire	O
units	O
in	O
the	O
execution	O
core	B-Device
.	O
</s>
<s>
This	O
lessened	O
pipeline	B-General_Concept
stalls	I-General_Concept
,	O
and	O
in	O
part	O
enabled	O
greater	O
speed-scaling	O
of	O
the	O
Pentium	B-Device
Pro	I-Device
and	O
successive	O
generations	O
of	O
CPUs	O
.	O
</s>
<s>
Superpipelining	O
,	O
which	O
increased	O
from	O
Pentium	B-General_Concept
's	O
5-stage	O
pipeline	O
to	O
14	O
of	O
the	O
Pentium	B-Device
Pro	I-Device
and	O
early	O
model	O
of	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
(	O
Coppermine	O
)	O
,	O
and	O
eventually	O
morphed	O
into	O
less	O
than	O
10-stage	O
pipeline	O
of	O
the	O
Pentium	B-Architecture
M	I-Architecture
for	O
embedded	O
and	O
mobile	O
market	O
due	O
to	O
energy	O
inefficiency	O
and	O
higher	O
voltage	O
issues	O
that	O
encountered	O
in	O
the	O
predecessor	O
,	O
and	O
then	O
again	O
lengthening	O
the	O
10	O
-	O
to	O
12-stage	O
pipeline	O
back	O
to	O
the	O
Core	B-Device
2	I-Device
due	O
to	O
facing	O
difficulty	O
increasing	O
clock	O
speed	O
while	O
improving	O
fabrication	O
process	O
can	O
somehow	O
negate	O
some	O
negative	O
impact	O
of	O
higher	O
power	O
consumption	O
on	O
the	O
deeper	O
pipeline	O
design	O
.	O
</s>
<s>
A	O
front-side	B-Architecture
bus	I-Architecture
using	O
a	O
variant	O
of	O
Gunning	B-General_Concept
transceiver	I-General_Concept
logic	I-General_Concept
to	O
enable	O
four	O
discrete	O
processors	O
to	O
share	O
system	O
resources	O
.	O
</s>
<s>
Physical	B-General_Concept
Address	I-General_Concept
Extension	I-General_Concept
(	O
PAE	O
)	O
and	O
a	O
wider	O
36-bit	O
address	O
bus	O
to	O
support	O
64	O
GB	O
of	O
physical	O
memory	O
.	O
</s>
<s>
Register	B-Architecture
renaming	I-Architecture
,	O
which	O
enabled	O
more	O
efficient	O
execution	O
of	O
multiple	O
instructions	B-Device
in	O
the	O
pipeline	O
.	O
</s>
<s>
CMOV	O
instructions	B-Device
,	O
which	O
are	O
heavily	O
used	O
in	O
compiler	B-Application
optimization	I-Application
.	O
</s>
<s>
Other	O
new	O
instructions	B-Device
:	O
FCMOV	O
,	O
FCOMI/FCOMIP/FUCOMI/FUCOMIP	O
,	O
RDPMC	O
,	O
UD2	O
.	O
</s>
<s>
New	O
instructions	B-Device
in	O
Pentium	B-General_Concept
II	I-General_Concept
Deschutes	B-General_Concept
core	B-Device
:	O
MMX	B-Architecture
,	O
FXSAVE	B-Device
,	O
FXRSTOR	O
.	O
</s>
<s>
New	O
instructions	B-Device
in	O
Pentium	B-General_Concept
III	I-General_Concept
:	O
Streaming	B-General_Concept
SIMD	I-General_Concept
Extensions	I-General_Concept
.	O
</s>
<s>
Upon	O
release	O
of	O
the	O
Pentium	O
4-M	O
and	O
Mobile	B-Architecture
Pentium	I-Architecture
4	I-General_Concept
,	O
it	O
was	O
quickly	O
realized	O
that	O
the	O
new	O
mobile	O
NetBurst	B-Device
processors	O
were	O
not	O
ideal	O
for	O
mobile	O
computing	O
.	O
</s>
<s>
NetBurst-based	O
processors	O
were	O
simply	O
not	O
as	O
efficient	O
per	O
clock	O
or	O
per	O
watt	O
compared	O
to	O
their	O
P6	B-Device
predecessors	O
.	O
</s>
<s>
Mobile	B-Architecture
Pentium	I-Architecture
4	O
processors	O
ran	O
much	O
hotter	O
than	O
Pentium	O
III-M	O
processors	O
without	O
significant	O
performance	O
advantages	O
.	O
</s>
<s>
The	O
result	O
was	O
a	O
modernized	O
P6	B-Device
design	O
called	O
the	O
Pentium	B-Architecture
M	I-Architecture
.	O
</s>
<s>
Quad-pumped	B-Device
front-side	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
With	O
the	O
initial	O
Banias	O
core	B-Device
,	O
Intel	O
adopted	O
the	O
400MT/s	O
FSB	B-Architecture
first	O
used	O
in	O
Pentium	B-General_Concept
4	I-General_Concept
.	O
</s>
<s>
The	O
Dothan	O
core	B-Device
moved	O
to	O
the	O
533MT/s	O
FSB	B-Architecture
,	O
following	O
Pentium	B-General_Concept
4	I-General_Concept
's	O
evolution	O
.	O
</s>
<s>
Larger	O
L1/L2	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Initially	O
1	O
MB	O
L2	O
cache	O
in	O
the	O
Banias	O
core	B-Device
,	O
then	O
2	O
MB	O
in	O
the	O
Dothan	O
core	B-Device
.	O
</s>
<s>
SSE2	B-General_Concept
Streaming	B-General_Concept
SIMD	I-General_Concept
Extensions	I-General_Concept
2	O
support	O
.	O
</s>
<s>
Micro-ops	B-General_Concept
Fusion	O
of	O
certain	O
sub-instructions	O
mediated	O
by	O
decoding	O
units	O
.	O
</s>
<s>
x86	B-Operating_System
commands	O
can	O
result	O
in	O
fewer	O
micro-operations	B-General_Concept
and	O
thus	O
require	O
fewer	O
processor	O
cycles	O
to	O
complete	O
.	O
</s>
<s>
The	O
Pentium	B-Architecture
M	I-Architecture
was	O
the	O
most	O
power	O
efficient	O
x86	B-Operating_System
processor	O
for	O
notebooks	O
for	O
several	O
years	O
,	O
consuming	O
a	O
maximum	O
of	O
27	O
watts	O
at	O
maximum	O
load	O
and	O
4-5	O
watts	O
while	O
idle	O
.	O
</s>
<s>
The	O
processing	O
efficiency	O
gains	O
brought	O
about	O
by	O
its	O
modernization	O
allowed	O
it	O
to	O
rival	O
the	O
Mobile	B-Architecture
Pentium	I-Architecture
4	O
clocked	O
over	O
1GHz	O
higher	O
(	O
the	O
fastest-clocked	O
Mobile	B-Architecture
Pentium	I-Architecture
4	O
compared	O
to	O
the	O
fastest-clocked	O
Pentium	B-Architecture
M	I-Architecture
)	O
and	O
equipped	O
with	O
much	O
more	O
memory	O
and	O
bus	O
bandwidth	O
.	O
</s>
<s>
The	O
first	O
Pentium	B-Architecture
M	I-Architecture
family	O
processors	O
(	O
"	O
Banias	O
"	O
)	O
internally	O
support	O
PAE	O
but	O
do	O
not	O
show	O
the	O
PAE	O
support	O
flag	O
in	O
their	O
CPUID	O
information	O
;	O
this	O
causes	O
some	O
operating	O
systems	O
(	O
primarily	O
Linux	O
distributions	O
)	O
to	O
refuse	O
to	O
boot	O
on	O
such	O
processors	O
since	O
PAE	O
support	O
is	O
required	O
in	O
their	O
kernels	O
.	O
</s>
<s>
The	O
Yonah	O
CPU	O
was	O
launched	O
in	O
January	O
2006	O
under	O
the	O
Core	B-Device
brand	O
.	O
</s>
<s>
Single	O
and	O
dual-core	O
mobile	O
version	O
were	O
sold	O
under	O
the	O
Core	B-Device
Solo	O
,	O
Core	B-Device
Duo	O
,	O
and	O
Pentium	B-Device
Dual-Core	I-Device
brands	O
,	O
and	O
a	O
server	O
version	O
was	O
released	O
as	O
Xeon	B-Device
LV	O
.	O
</s>
<s>
These	O
processors	O
provided	O
partial	O
solutions	O
to	O
some	O
of	O
the	O
Pentium	B-Architecture
M	I-Architecture
's	O
shortcomings	O
by	O
adding	O
:	O
</s>
<s>
Increased	O
FSB	B-Architecture
speed	O
,	O
with	O
the	O
FSB	B-Architecture
running	O
at	O
533MT/s	O
or	O
667MT/s	O
.	O
</s>
<s>
This	O
resulted	O
in	O
the	O
interim	O
microarchitecture	B-General_Concept
for	O
low-voltage	O
only	O
CPUs	O
,	O
part	O
way	O
between	O
P6	B-Device
and	O
the	O
following	O
Core	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
On	O
July	O
27	O
,	O
2006	O
,	O
the	O
Core	B-Device
microarchitecture	I-Device
,	O
a	O
derivative	O
of	O
P6	B-Device
,	O
was	O
launched	O
in	O
form	O
of	O
the	O
Core	B-Device
2	I-Device
processor	O
.	O
</s>
<s>
Subsequently	O
,	O
more	O
processors	O
were	O
released	O
with	O
the	O
Core	B-Device
microarchitecture	I-Device
under	O
Core	B-Device
2	I-Device
,	O
Xeon	B-Device
,	O
Pentium	B-General_Concept
and	O
Celeron	B-Device
brand	O
names	O
.	O
</s>
<s>
The	O
Core	B-Device
microarchitecture	I-Device
is	O
Intel	O
's	O
final	O
mainstream	O
processor	O
line	O
to	O
use	O
FSB	B-Architecture
,	O
with	O
all	O
later	O
Intel	O
processors	O
based	O
on	O
Nehalem	B-Device
and	O
later	O
Intel	O
microarchitectures	B-General_Concept
featuring	O
an	O
integrated	O
memory	O
controller	O
and	O
a	O
QPI	B-Architecture
or	O
DMI	B-Architecture
bus	O
for	O
communication	O
with	O
the	O
rest	O
of	O
the	O
system	O
.	O
</s>
<s>
Improvements	O
relative	O
to	O
the	O
Intel	B-Device
Core	I-Device
processors	O
were	O
:	O
</s>
<s>
SSE4.1	O
support	O
for	O
all	O
Core	B-Device
2	I-Device
models	O
manufactured	O
at	O
a	O
45nm	O
lithography	O
.	O
</s>
<s>
Support	O
for	O
the	O
64-bit	O
x86-64	O
architecture	O
,	O
which	O
was	O
previously	O
only	O
offered	O
by	O
Prescott	O
processors	O
,	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
last	O
architectural	O
installment	O
.	O
</s>
<s>
Increased	O
FSB	B-Architecture
speed	O
,	O
ranging	O
from	O
533MT/s	O
to	O
1600MT/s	O
.	O
</s>
<s>
Increased	O
L2	O
cache	O
size	O
,	O
with	O
the	O
L2	O
cache	O
size	O
ranging	O
from	O
1	O
MB	O
to	O
12	O
MB	O
(	O
Core	B-Device
2	I-Device
Duo	O
processors	O
use	O
a	O
shared	O
L2	O
cache	O
while	O
Core	B-Device
2	I-Device
Quad	O
processors	O
having	O
half	O
of	O
the	O
total	O
cache	O
is	O
shared	O
by	O
each	O
core	B-Device
pair	O
)	O
.	O
</s>
<s>
Dynamic	O
Front	B-Architecture
Side	I-Architecture
Bus	I-Architecture
Throttling	O
(	O
some	O
mobile	O
models	O
)	O
,	O
where	O
the	O
speed	O
of	O
the	O
FSB	B-Architecture
is	O
reduced	O
in	O
half	O
,	O
which	O
by	O
extension	O
reduces	O
the	O
processor	O
's	O
speed	O
in	O
half	O
.	O
</s>
<s>
Dynamic	O
Acceleration	O
Technology	O
for	O
some	O
mobile	O
Core	B-Device
2	I-Device
Duo	O
processors	O
,	O
and	O
Dual	O
Dynamic	O
Acceleration	O
Technology	O
for	O
mobile	O
Core	B-Device
2	I-Device
Quad	O
processors	O
.	O
</s>
<s>
Dynamic	O
Acceleration	O
Technology	O
allows	O
the	O
CPU	O
to	O
overclock	O
one	O
processor	O
core	B-Device
while	O
turning	O
off	O
the	O
one	O
.	O
</s>
<s>
This	O
feature	O
is	O
triggered	O
when	O
an	O
application	O
only	O
uses	O
a	O
single	O
core	B-Device
for	O
Core	B-Device
2	I-Device
Duo	O
or	O
up	O
to	O
two	O
cores	O
for	O
Core	B-Device
2	I-Device
Quad	O
.	O
</s>
<s>
While	O
all	O
these	O
chips	O
are	O
technically	O
derivatives	O
of	O
the	O
Pentium	B-Device
Pro	I-Device
,	O
the	O
architecture	O
has	O
gone	O
through	O
several	O
radical	O
changes	O
since	O
its	O
inception	O
.	O
</s>
