<s>
Opteron	B-General_Concept
is	O
AMD	O
's	O
x86	B-Operating_System
former	O
server	B-Application
and	O
workstation	B-Device
processor	B-Architecture
line	O
,	O
and	O
was	O
the	O
first	O
processor	B-Architecture
which	O
supported	O
the	O
AMD64	B-Device
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
known	O
generically	O
as	O
x86-64	B-Device
)	O
.	O
</s>
<s>
It	O
was	O
released	O
on	O
April	O
22	O
,	O
2003	O
,	O
with	O
the	O
SledgeHammer	O
core	O
(	O
K8	O
)	O
and	O
was	O
intended	O
to	O
compete	O
in	O
the	O
server	B-Application
and	O
workstation	B-Device
markets	O
,	O
particularly	O
in	O
the	O
same	O
segment	O
as	O
the	O
Intel	B-Device
Xeon	I-Device
processor	B-Architecture
.	O
</s>
<s>
Processors	O
based	O
on	O
the	O
AMD	O
K10	O
microarchitecture	O
(	O
codenamed	O
Barcelona	O
)	O
were	O
announced	O
on	O
September	O
10	O
,	O
2007	O
,	O
featuring	O
a	O
new	O
quad-core	B-Architecture
configuration	O
.	O
</s>
<s>
The	O
most-recently	O
released	O
Opteron	B-General_Concept
CPUs	B-General_Concept
are	O
the	O
Piledriver-based	O
Opteron	B-General_Concept
4300	O
and	O
6300	O
series	O
processors	O
,	O
codenamed	O
"	O
Seoul	O
"	O
and	O
"	O
Abu	O
Dhabi	O
"	O
respectively	O
.	O
</s>
<s>
In	O
January	O
2016	O
,	O
the	O
first	O
ARMv8-A	O
based	O
Opteron-branded	O
SoC	O
was	O
released	O
,	O
though	O
it	O
is	O
unclear	O
what	O
,	O
if	O
any	O
,	O
heritage	O
this	O
Opteron-branded	O
product	O
line	O
shares	O
with	O
the	O
original	O
Opteron	B-General_Concept
technology	O
other	O
than	O
intended	O
use	O
in	O
the	O
server	B-Application
space	O
.	O
</s>
<s>
Opteron	B-General_Concept
combines	O
two	O
important	O
capabilities	O
in	O
a	O
single	O
processor	B-Architecture
:	O
</s>
<s>
The	O
first	O
capability	O
is	O
notable	O
because	O
at	O
the	O
time	O
of	O
Opteron	B-General_Concept
's	O
introduction	O
,	O
the	O
only	O
other	O
64-bit	B-Device
architecture	I-Device
marketed	O
with	O
32-bit	O
x86	B-Operating_System
compatibility	O
(	O
Intel	O
's	O
Itanium	B-General_Concept
)	O
ran	O
x86	B-Operating_System
legacy-applications	O
only	O
with	O
significant	O
speed	O
degradation	O
.	O
</s>
<s>
The	O
second	O
capability	O
,	O
by	O
itself	O
,	O
is	O
less	O
noteworthy	O
,	O
as	O
major	O
RISC	B-Architecture
architectures	I-Architecture
(	O
such	O
as	O
SPARC	B-Architecture
,	O
Alpha	B-Device
,	O
PA-RISC	B-Device
,	O
PowerPC	B-Architecture
,	O
MIPS	B-Device
)	O
have	O
been	O
64-bit	B-Device
for	O
many	O
years	O
.	O
</s>
<s>
In	O
combining	O
these	O
two	O
capabilities	O
,	O
however	O
,	O
the	O
Opteron	B-General_Concept
earned	O
recognition	O
for	O
its	O
ability	O
to	O
run	O
the	O
vast	O
installed	O
base	O
of	O
x86	B-Operating_System
applications	O
economically	O
,	O
while	O
simultaneously	O
offering	O
an	O
upgrade	O
path	O
to	O
64-bit	B-Device
computing	I-Device
.	O
</s>
<s>
The	O
Opteron	B-General_Concept
processor	B-Architecture
possesses	O
an	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
supporting	O
DDR	O
SDRAM	O
,	O
DDR2	O
SDRAM	O
or	O
DDR3	O
SDRAM	O
(	O
depending	O
on	O
processor	B-Architecture
generation	O
)	O
.	O
</s>
<s>
This	O
both	O
reduces	O
the	O
latency	O
penalty	O
for	O
accessing	O
the	O
main	O
RAM	B-Architecture
and	O
eliminates	O
the	O
need	O
for	O
a	O
separate	O
northbridge	B-Device
chip	I-Device
.	O
</s>
<s>
In	O
multi-processor	O
systems	O
(	O
more	O
than	O
one	O
Opteron	B-General_Concept
on	O
a	O
single	O
motherboard	B-Device
)	O
,	O
the	O
CPUs	B-General_Concept
communicate	O
using	O
the	O
Direct	O
Connect	O
Architecture	O
over	O
high-speed	O
HyperTransport	B-Device
links	O
.	O
</s>
<s>
Each	O
CPU	O
can	O
access	O
the	O
main	O
memory	O
of	O
another	O
processor	B-Architecture
,	O
transparent	O
to	O
the	O
programmer	O
.	O
</s>
<s>
The	O
Opteron	B-General_Concept
approach	O
to	O
multi-processing	O
is	O
not	O
the	O
same	O
as	O
standard	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
;	O
instead	O
of	O
having	O
one	O
bank	O
of	O
memory	O
for	O
all	O
CPUs	B-General_Concept
,	O
each	O
CPU	O
has	O
its	O
own	O
memory	O
.	O
</s>
<s>
Thus	O
the	O
Opteron	B-General_Concept
is	O
a	O
Non-Uniform	B-Operating_System
Memory	I-Operating_System
Access	I-Operating_System
(	O
NUMA	O
)	O
architecture	O
.	O
</s>
<s>
The	O
Opteron	B-General_Concept
CPU	O
directly	O
supports	O
up	O
to	O
an	O
8-way	O
configuration	O
,	O
which	O
can	O
be	O
found	O
in	O
mid-level	O
servers	O
.	O
</s>
<s>
Enterprise-level	O
servers	O
use	O
additional	O
(	O
and	O
expensive	O
)	O
routing	O
chips	O
to	O
support	O
more	O
than	O
8	O
CPUs	B-General_Concept
per	O
box	O
.	O
</s>
<s>
In	O
a	O
variety	O
of	O
computing	O
benchmarks	O
,	O
the	O
Opteron	B-General_Concept
architecture	O
has	O
demonstrated	O
better	O
multi-processor	O
scaling	O
than	O
the	O
Intel	B-Device
Xeon	I-Device
which	O
did	O
n't	O
have	O
a	O
point	O
to	O
point	O
system	O
until	O
QPI	O
and	O
integrated	B-General_Concept
memory	I-General_Concept
controllers	I-General_Concept
with	O
the	O
Nehalem	O
design	O
.	O
</s>
<s>
This	O
is	O
primarily	O
because	O
adding	O
another	O
Opteron	B-General_Concept
processor	B-Architecture
increases	O
memory	O
bandwidth	O
,	O
while	O
that	O
is	O
not	O
always	O
the	O
case	O
for	O
Xeon	B-Device
systems	O
,	O
and	O
the	O
fact	O
that	O
the	O
Opterons	B-General_Concept
use	O
a	O
switched	B-Architecture
fabric	I-Architecture
,	O
rather	O
than	O
a	O
shared	O
bus	B-General_Concept
.	O
</s>
<s>
In	O
particular	O
,	O
the	O
Opteron	B-General_Concept
's	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
allows	O
the	O
CPU	O
to	O
access	O
local	O
RAM	B-Architecture
very	O
quickly	O
.	O
</s>
<s>
In	O
contrast	O
,	O
multiprocessor	O
Xeon	B-Device
system	O
CPUs	B-General_Concept
share	O
only	O
two	O
common	O
buses	O
for	O
both	O
processor-processor	O
and	O
processor-memory	O
communication	O
.	O
</s>
<s>
As	O
the	O
number	O
of	O
CPUs	B-General_Concept
increases	O
in	O
a	O
typical	O
Xeon	B-Device
system	O
,	O
contention	B-Architecture
for	O
the	O
shared	O
bus	B-General_Concept
causes	O
computing	O
efficiency	O
to	O
drop	O
.	O
</s>
<s>
Intel	O
migrated	O
to	O
a	O
memory	O
architecture	O
similar	O
to	O
the	O
Opteron	B-General_Concept
's	O
for	O
the	O
Intel	B-Device
Core	I-Device
i7	I-Device
family	O
of	O
processors	O
and	O
their	O
Xeon	B-Device
derivatives	O
.	O
</s>
<s>
In	O
April	O
2005	O
,	O
AMD	O
introduced	O
its	O
first	O
multi-core	B-Architecture
Opterons	B-General_Concept
.	O
</s>
<s>
At	O
the	O
time	O
,	O
AMD	O
's	O
use	O
of	O
the	O
term	O
multi-core	B-Architecture
in	O
practice	O
meant	O
dual-core	B-Architecture
;	O
each	O
physical	O
Opteron	B-General_Concept
chip	O
contained	O
two	O
processor	B-Architecture
cores	O
.	O
</s>
<s>
This	O
effectively	O
doubled	O
the	O
computing	O
performance	O
available	O
to	O
each	O
motherboard	B-Device
processor	B-Architecture
socket	O
.	O
</s>
<s>
Because	O
motherboard	B-Device
costs	O
increase	O
dramatically	O
as	O
the	O
number	O
of	O
CPU	O
sockets	O
increase	O
,	O
multicore	B-Architecture
CPUs	I-Architecture
enable	O
a	O
multiprocessing	O
system	O
to	O
be	O
built	O
at	O
lower	O
cost	O
.	O
</s>
<s>
AMD	O
's	O
model	O
number	O
scheme	O
has	O
changed	O
somewhat	O
in	O
light	O
of	O
its	O
new	O
multicore	B-Architecture
lineup	O
.	O
</s>
<s>
At	O
the	O
time	O
of	O
its	O
introduction	O
,	O
AMD	O
's	O
fastest	O
multicore	B-Architecture
Opteron	B-General_Concept
was	O
the	O
model	O
875	O
,	O
with	O
two	O
cores	O
running	O
at	O
2.2	O
GHz	O
each	O
.	O
</s>
<s>
AMD	O
's	O
fastest	O
single-core	O
Opteron	B-General_Concept
at	O
this	O
time	O
was	O
the	O
model	O
252	O
,	O
with	O
one	O
core	O
running	O
at	O
2.6GHz	O
.	O
</s>
<s>
For	O
multithreaded	B-General_Concept
applications	O
,	O
or	O
many	O
single	O
threaded	O
applications	O
,	O
the	O
model	O
875	O
would	O
be	O
much	O
faster	O
than	O
the	O
model	O
252	O
.	O
</s>
<s>
Second-generation	O
Opterons	B-General_Concept
are	O
offered	O
in	O
three	O
series	O
:	O
the	O
1000	O
Series	O
(	O
single	O
socket	O
only	O
)	O
,	O
the	O
2000	O
Series	O
(	O
dual	O
socket-capable	O
)	O
,	O
and	O
the	O
8000	O
Series	O
(	O
quad	O
or	O
octo	O
socket-capable	O
)	O
.	O
</s>
<s>
Earlier	O
dual	B-Architecture
core	I-Architecture
DDR2	O
based	O
platforms	O
were	O
upgradeable	O
to	O
quad	B-Architecture
core	I-Architecture
chips	O
.	O
</s>
<s>
The	O
fourth	O
generation	O
was	O
announced	O
in	O
June	O
2009	O
with	O
the	O
Istanbul	O
hexa-cores	B-Architecture
.	O
</s>
<s>
In	O
March	O
2010	O
AMD	O
released	O
the	O
Magny-Cours	O
Opteron	B-General_Concept
6100	O
series	O
CPUs	B-General_Concept
for	O
Socket	O
G34	O
.	O
</s>
<s>
These	O
are	O
8	O
-	O
and	O
12-core	O
multi-chip	B-Algorithm
module	I-Algorithm
CPUs	B-General_Concept
consisting	O
of	O
two	O
four	O
or	O
six-core	O
dies	O
with	O
a	O
HyperTransport	B-Device
3.1	O
link	O
connecting	O
the	O
two	O
dies	O
.	O
</s>
<s>
These	O
CPUs	B-General_Concept
updated	O
the	O
multi-socket	O
Opteron	B-General_Concept
platform	O
to	O
use	O
DDR3	O
memory	O
and	O
increased	O
the	O
maximum	O
HyperTransport	B-Device
link	O
speed	O
from	O
2.40GHz	O
(	O
4.80GT/s	O
)	O
for	O
the	O
Istanbul	O
CPUs	B-General_Concept
to	O
3.20GHz	O
(	O
6.40GT/s	O
)	O
.	O
</s>
<s>
AMD	O
changed	O
the	O
naming	O
scheme	O
for	O
its	O
Opteron	B-General_Concept
models	O
.	O
</s>
<s>
Opteron	B-General_Concept
4000	O
series	O
CPUs	B-General_Concept
on	O
Socket	O
C32	O
(	O
released	O
July	O
2010	O
)	O
are	O
dual-socket	O
capable	O
and	O
are	O
targeted	O
at	O
uniprocessor	O
and	O
dual-processor	O
uses	O
.	O
</s>
<s>
The	O
Opteron	B-General_Concept
6000	O
series	O
CPUs	B-General_Concept
on	O
Socket	O
G34	O
are	O
quad-socket	O
capable	O
and	O
are	O
targeted	O
at	O
high-end	O
dual-processor	O
and	O
quad-processor	O
applications	O
.	O
</s>
<s>
AMD	O
released	O
Socket	O
939	O
Opterons	B-General_Concept
,	O
reducing	O
the	O
cost	O
of	O
motherboards	B-Device
for	O
low-end	O
servers	O
and	O
workstations	B-Device
.	O
</s>
<s>
Except	O
for	O
the	O
fact	O
they	O
have	O
1MB	O
L2	O
cache	O
(	O
versus	O
512KB	O
for	O
the	O
Athlon	O
64	O
)	O
the	O
Socket	O
939	O
Opterons	B-General_Concept
are	O
identical	O
to	O
the	O
San	O
Diego	O
and	O
Toledo	O
core	O
Athlon	O
64s	O
,	O
but	O
are	O
run	O
at	O
lower	O
clock	O
speeds	O
than	O
the	O
cores	O
are	O
capable	O
of	O
,	O
making	O
them	O
more	O
stable	O
.	O
</s>
<s>
Socket	O
AM2	O
Opterons	B-General_Concept
are	O
available	O
for	O
servers	O
that	O
only	O
have	O
a	O
single-chip	O
setup	O
.	O
</s>
<s>
F	O
dual	B-Architecture
core	I-Architecture
AM2	O
Opterons	B-General_Concept
feature	O
2	O
×	O
1MB	O
L2	O
cache	O
,	O
unlike	O
the	O
majority	O
of	O
their	O
Athlon	O
64	O
X2	O
cousins	O
which	O
feature	O
2	O
×	O
512KB	O
L2	O
cache	O
.	O
</s>
<s>
These	O
CPUs	B-General_Concept
are	O
given	O
model	O
numbers	O
ranging	O
from	O
1210	O
to	O
1224	O
.	O
</s>
<s>
AMD	O
introduced	O
three	O
quad-core	B-Architecture
Opterons	B-General_Concept
on	O
Socket	O
AM2+	O
for	O
single-CPU	O
servers	O
in	O
2007	O
.	O
</s>
<s>
These	O
CPUs	B-General_Concept
are	O
produced	O
on	O
a	O
65nm	O
manufacturing	O
process	B-Architecture
and	O
are	O
similar	O
to	O
the	O
Agena	O
Phenom	O
X4	O
CPUs	B-General_Concept
.	O
</s>
<s>
The	O
Socket	O
AM2+	O
quad-core	B-Architecture
Opterons	B-General_Concept
are	O
code-named	O
"	O
Budapest	O
"	O
.	O
</s>
<s>
The	O
Socket	O
AM2+	O
Opterons	B-General_Concept
carry	O
model	O
numbers	O
of	O
1352	O
(	O
2.10GHz	O
)	O
,	O
1354	O
(	O
2.20GHz	O
)	O
,	O
and	O
1356	O
(	O
2.30GHz	O
)	O
.	O
</s>
<s>
AMD	O
introduced	O
three	O
quad-core	B-Architecture
Opterons	B-General_Concept
on	O
Socket	O
AM3	O
for	O
single-CPU	O
servers	O
in	O
2009	O
.	O
</s>
<s>
These	O
CPUs	B-General_Concept
are	O
produced	O
on	O
a	O
45nm	O
manufacturing	O
process	B-Architecture
and	O
are	O
similar	O
to	O
the	O
Deneb-based	O
Phenom	O
II	O
X4	O
CPUs	B-General_Concept
.	O
</s>
<s>
The	O
Socket	O
AM3	O
quad-core	B-Architecture
Opterons	B-General_Concept
are	O
code-named	O
"	O
Suzuka	O
"	O
.	O
</s>
<s>
These	O
CPUs	B-General_Concept
carry	O
model	O
numbers	O
of	O
1381	O
(	O
2.50GHz	O
)	O
,	O
1385	O
(	O
2.70GHz	O
)	O
,	O
and	O
1389	O
(	O
2.90GHz	O
)	O
.	O
</s>
<s>
Opteron	B-General_Concept
CPUs	B-General_Concept
in	O
the	O
AM3+	O
package	O
are	O
named	O
Opteron	B-General_Concept
3xxx	O
.	O
</s>
<s>
Socket	O
F	O
(	O
LGA	B-Algorithm
1207	O
contacts	O
)	O
is	O
AMD	O
’s	O
second	O
generation	O
of	O
Opteron	B-General_Concept
socket	O
.	O
</s>
<s>
the	O
"	O
lidded	O
land	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
"	O
socket	O
adds	O
support	O
for	O
DDR2	O
SDRAM	O
and	O
improved	O
HyperTransport	B-Device
version	O
3	O
connectivity	O
.	O
</s>
<s>
Physically	O
the	O
socket	O
and	O
processor	B-Architecture
package	O
are	O
nearly	O
identical	O
,	O
although	O
not	O
generally	O
compatible	O
with	O
socket	O
1207	O
FX	O
.	O
</s>
<s>
Socket	O
G34	O
(	O
LGA	B-Algorithm
1944	O
contacts	O
)	O
is	O
one	O
of	O
the	O
third	O
generation	O
of	O
Opteron	B-General_Concept
sockets	O
,	O
along	O
with	O
Socket	O
C32	O
.	O
</s>
<s>
This	O
socket	O
supports	O
Magny-Cours	O
Opteron	B-General_Concept
6100	O
,	O
Bulldozer-based	O
Interlagos	O
Opteron	B-General_Concept
6200	O
,	O
and	O
Piledriver-based	O
"	O
Abu	O
Dhabi	O
"	O
Opteron	B-General_Concept
6300	O
series	O
processors	O
.	O
</s>
<s>
Unlike	O
previous	O
multi-CPU	O
Opteron	B-General_Concept
sockets	O
,	O
Socket	O
G34	O
CPUs	B-General_Concept
will	O
function	O
with	O
unbuffered	O
ECC	B-Error_Name
or	O
non-ECC	O
RAM	B-Architecture
in	O
addition	O
to	O
the	O
traditional	O
registered	O
ECC	B-Error_Name
RAM	B-Architecture
.	O
</s>
<s>
Socket	O
C32	O
(	O
LGA	B-Algorithm
1207	O
contacts	O
)	O
is	O
the	O
other	O
member	O
of	O
the	O
third	O
generation	O
of	O
Opteron	B-General_Concept
sockets	O
.	O
</s>
<s>
This	O
socket	O
is	O
physically	O
similar	O
to	O
Socket	O
F	O
but	O
is	O
not	O
compatible	O
with	O
Socket	O
F	O
CPUs	B-General_Concept
.	O
</s>
<s>
Socket	O
C32	O
uses	O
DDR3	O
SDRAM	O
and	O
is	O
keyed	O
differently	O
so	O
as	O
to	O
prevent	O
the	O
insertion	O
of	O
Socket	O
F	O
CPUs	B-General_Concept
that	O
can	O
use	O
only	O
DDR2	O
SDRAM	O
.	O
</s>
<s>
Like	O
Socket	O
G34	O
,	O
Socket	O
C32	O
CPUs	B-General_Concept
will	O
be	O
able	O
to	O
use	O
unbuffered	O
ECC	B-Error_Name
or	O
non-ECC	O
RAM	B-Architecture
in	O
addition	O
to	O
registered	O
ECC	B-Error_Name
SDRAM	O
.	O
</s>
<s>
The	O
Opteron	B-General_Concept
line	O
saw	O
an	O
update	O
with	O
the	O
implementation	O
of	O
the	O
AMD	O
K10	O
microarchitecture	O
.	O
</s>
<s>
New	O
processors	O
,	O
launched	O
in	O
the	O
third	O
quarter	O
of	O
2007	O
(	O
codename	O
Barcelona	O
)	O
,	O
incorporate	O
a	O
variety	O
of	O
improvements	O
,	O
particularly	O
in	O
memory	O
prefetching	O
,	O
speculative	O
loads	O
,	O
SIMD	B-Device
execution	O
and	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
yielding	O
an	O
appreciable	O
performance	O
improvement	O
over	O
K8-based	O
Opterons	B-General_Concept
,	O
within	O
the	O
same	O
power	O
envelope	O
.	O
</s>
<s>
In	O
2007	O
AMD	O
introduced	O
a	O
scheme	O
to	O
characterize	O
the	O
power	O
consumption	O
of	O
new	O
processors	O
under	O
"	O
average	O
"	O
daily	O
usage	O
,	O
named	O
average	B-General_Concept
CPU	I-General_Concept
power	I-General_Concept
(	O
ACP	O
)	O
.	O
</s>
<s>
The	O
Opteron	B-General_Concept
X1150	O
and	O
Opteron	B-General_Concept
X2150	O
APU	O
are	O
used	O
with	O
the	O
BGA-769	O
or	O
Socket	O
FT3	O
.	O
</s>
<s>
For	O
Socket	O
940	O
and	O
Socket	O
939	O
Opterons	B-General_Concept
,	O
each	O
chip	O
has	O
a	O
three-digit	O
model	O
number	O
,	O
in	O
the	O
form	O
Opteron	B-General_Concept
XYY	O
.	O
</s>
<s>
For	O
Socket	O
F	O
and	O
Socket	O
AM2	O
Opterons	B-General_Concept
,	O
each	O
chip	O
has	O
a	O
four-digit	O
model	O
number	O
,	O
in	O
the	O
form	O
Opteron	B-General_Concept
XZYY	O
.	O
</s>
<s>
For	O
all	O
first	O
,	O
second	O
,	O
and	O
third-generation	O
Opterons	B-General_Concept
,	O
the	O
first	O
digit	O
(	O
the	O
X	O
)	O
specifies	O
the	O
number	O
of	O
CPUs	B-General_Concept
on	O
the	O
target	O
machine	O
:	O
</s>
<s>
For	O
Socket	O
F	O
and	O
Socket	O
AM2	O
Opterons	B-General_Concept
,	O
the	O
second	O
digit	O
(	O
the	O
Z	O
)	O
represents	O
the	O
processor	B-Architecture
generation	O
.	O
</s>
<s>
Presently	O
,	O
only	O
2	O
(	O
dual-core	B-Architecture
,	O
DDR2	O
)	O
,	O
3	O
(	O
quad-core	B-Architecture
,	O
DDR2	O
)	O
and	O
4	O
(	O
six-core	O
,	O
DDR2	O
)	O
are	O
used	O
.	O
</s>
<s>
Socket	O
C32	O
and	O
G34	O
Opterons	B-General_Concept
use	O
a	O
new	O
four-digit	O
numbering	O
scheme	O
.	O
</s>
<s>
The	O
first	O
digit	O
refers	O
to	O
the	O
number	O
of	O
CPUs	B-General_Concept
in	O
the	O
target	O
machine	O
:	O
</s>
<s>
4	O
–	O
Designed	O
for	O
uniprocessor	O
and	O
dual-processor	O
systems	O
.	O
</s>
<s>
6	O
–	O
Designed	O
for	O
dual-processor	O
and	O
four-processor	O
systems	O
.	O
</s>
<s>
Like	O
the	O
previous	O
second	O
and	O
third	O
generation	O
Opterons	B-General_Concept
,	O
the	O
second	O
number	O
refers	O
to	O
the	O
processor	B-Architecture
generation	O
.	O
</s>
<s>
For	O
all	O
Opterons	B-General_Concept
,	O
the	O
last	O
two	O
digits	O
in	O
the	O
model	O
number	O
(	O
the	O
YY	O
)	O
indicate	O
the	O
clock	O
frequency	O
of	O
a	O
CPU	O
,	O
a	O
higher	O
number	O
indicating	O
a	O
higher	O
clock	O
frequency	O
.	O
</s>
<s>
This	O
speed	O
indication	O
is	O
comparable	O
to	O
processors	O
of	O
the	O
same	O
generation	O
if	O
they	O
have	O
the	O
same	O
amount	O
of	O
cores	O
,	O
single-cores	O
and	O
dual-cores	B-Architecture
have	O
different	O
indications	O
despite	O
sometimes	O
having	O
the	O
same	O
clock	O
frequency	O
.	O
</s>
<s>
The	O
suffix	O
HE	O
or	O
EE	O
indicates	O
a	O
high-efficiency/energy	O
-efficiency	O
model	O
having	O
a	O
lower	O
TDP	B-General_Concept
than	O
a	O
standard	O
Opteron	B-General_Concept
.	O
</s>
<s>
The	O
suffix	O
SE	O
indicates	O
a	O
top-of-the-line	O
model	O
having	O
a	O
higher	O
TDP	B-General_Concept
than	O
a	O
standard	O
Opteron	B-General_Concept
.	O
</s>
<s>
Starting	O
from	O
65nm	O
fabrication	B-Architecture
process	I-Architecture
,	O
the	O
Opteron	B-General_Concept
codenames	O
have	O
been	O
based	O
on	O
Formula	B-Application
1	I-Application
hosting	O
cities	O
;	O
AMD	O
has	O
a	O
long	O
term	O
sponsorship	O
with	O
F1	O
's	O
most	O
successful	O
team	O
,	O
Ferrari	O
.	O
</s>
<s>
64-bit	B-Device
segment	O
limit	O
checks	O
for	O
VMware-style	O
binary-translation	O
virtualization	B-General_Concept
.	O
</s>
<s>
The	O
Opteron	B-General_Concept
A1100-series	O
"	O
Seattle	O
"	O
(	O
28nm	O
)	O
are	O
SoCs	O
based	O
on	O
ARM	O
Cortex-A57	O
cores	O
that	O
use	O
the	O
ARMv8-A	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Opteron	B-General_Concept
processors	O
first	O
appeared	O
in	O
the	O
top	O
100	O
systems	O
of	O
the	O
fastest	B-Operating_System
supercomputers	I-Operating_System
in	I-Operating_System
the	I-Operating_System
world	I-Operating_System
list	O
in	O
the	O
early	O
2000s	O
.	O
</s>
<s>
By	O
the	O
summer	O
of	O
2006	O
,	O
21	O
of	O
the	O
top	O
100	O
systems	O
used	O
Opteron	B-General_Concept
processors	O
,	O
and	O
in	O
the	O
November	O
2010	O
and	O
June	O
2011	O
lists	O
the	O
Opteron	B-General_Concept
reached	O
its	O
maximum	O
representation	O
of	O
33	O
of	O
the	O
top	O
100	O
systems	O
.	O
</s>
<s>
The	O
number	O
of	O
Opteron-based	O
systems	O
decreased	O
fairly	O
rapidly	O
after	O
this	O
peak	O
,	O
falling	O
to	O
3	O
of	O
the	O
top	O
100	O
systems	O
by	O
November	O
2016	O
,	O
and	O
in	O
November	O
2017	O
only	O
one	O
Opteron-based	O
system	O
remained	O
.	O
</s>
<s>
Several	O
supercomputers	O
using	O
only	O
Opteron	B-General_Concept
processors	O
were	O
ranked	O
in	O
the	O
top	O
10	O
systems	O
between	O
2003	O
and	O
2015	O
,	O
notably	O
:	O
</s>
<s>
Other	O
top	O
10	O
systems	O
using	O
a	O
combination	O
of	O
Opteron	B-General_Concept
processors	O
and	O
compute	O
accelerators	O
have	O
included	O
:	O
</s>
<s>
IBM	B-General_Concept
Roadrunner	I-General_Concept
–	O
Los	O
Alamos	O
National	O
Laboratory	O
–	O
system	O
in	O
2008	O
.	O
</s>
<s>
Composed	O
of	O
Opteron	B-General_Concept
processors	O
with	O
IBM	O
PowerXCell	B-General_Concept
8i	I-General_Concept
co-processors	O
.	O
</s>
<s>
The	O
only	O
system	O
remaining	O
on	O
the	O
list	O
(	O
as	O
of	O
November	O
2017	O
)	O
,	O
also	O
using	O
Opteron	B-General_Concept
processors	O
combined	O
with	O
compute	O
accelerators	O
:	O
</s>
<s>
Titan	B-Device
(	O
supercomputer	O
)	O
–	O
Oak	O
Ridge	O
National	O
Laboratory	O
–	O
system	O
in	O
2012	O
,	O
as	O
of	O
November	O
2017	O
.	O
</s>
<s>
Composed	O
of	O
Opteron	B-General_Concept
processors	O
with	O
Nvidia	B-General_Concept
Fermi	I-General_Concept
(	O
microarchitecture	O
)	O
GPU-based	O
accelerators	O
.	O
</s>
<s>
AMD	O
released	O
some	O
Opteron	B-General_Concept
processors	O
without	O
Optimized	O
Power	O
Management	O
(	O
OPM	O
)	O
support	O
,	O
which	O
use	O
DDR	O
memory	O
.	O
</s>
<s>
AMD	O
recalled	O
some	O
E4	O
stepping-revision	O
single-core	O
Opteron	B-General_Concept
processors	O
,	O
including	O
×52	O
(	O
2.6GHz	O
)	O
and	O
×54	O
(	O
2.8GHz	O
)	O
models	O
which	O
use	O
DDR	O
memory	O
.	O
</s>
<s>
The	O
following	O
table	O
describes	O
affected	O
processors	O
,	O
as	O
listed	O
in	O
AMD	B-General_Concept
Opteron	I-General_Concept
×52	O
and	O
×54	O
Production	O
Notice	O
of	O
2006	O
.	O
</s>
<s>
A	O
software	O
verification	O
tool	O
for	O
identifying	O
the	O
AMD	B-General_Concept
Opteron	I-General_Concept
processors	O
listed	O
in	O
the	O
above	O
table	O
that	O
may	O
be	O
affected	O
under	O
these	O
specific	O
conditions	O
is	O
available	O
,	O
only	O
to	O
AMD	O
OEM	O
partners	O
.	O
</s>
<s>
In	O
the	O
February	O
2010	O
issue	O
of	O
Custom	O
PC	O
(	O
a	O
UK-based	O
computing	O
magazine	O
focused	O
on	O
PC	O
hardware	O
)	O
,	O
the	O
AMD	B-General_Concept
Opteron	I-General_Concept
144	O
(	O
released	O
in	O
Summer	O
2005	O
)	O
appeared	O
in	O
the	O
"	O
Hardware	O
Hall	O
of	O
Fame	O
"	O
.	O
</s>
