<s>
Operand	B-General_Concept
forwarding	I-General_Concept
(	O
or	O
data	B-General_Concept
forwarding	I-General_Concept
)	O
is	O
an	O
optimization	O
in	O
pipelined	B-General_Concept
CPUs	B-Device
to	O
limit	O
performance	O
deficits	O
which	O
occur	O
due	O
to	O
pipeline	B-General_Concept
stalls	I-General_Concept
.	O
</s>
<s>
A	O
data	O
hazard	O
can	O
lead	O
to	O
a	O
pipeline	B-General_Concept
stall	I-General_Concept
when	O
the	O
current	O
operation	O
has	O
to	O
wait	O
for	O
the	O
results	O
of	O
an	O
earlier	O
operation	O
which	O
has	O
not	O
yet	O
finished	O
.	O
</s>
<s>
If	O
these	O
two	O
assembly	B-Language
pseudocode	O
instructions	O
run	O
in	O
a	O
pipeline	B-General_Concept
,	O
after	O
fetching	O
and	O
decoding	O
the	O
second	O
instruction	O
,	O
the	O
pipeline	B-General_Concept
stalls	I-General_Concept
,	O
waiting	O
until	O
the	O
result	O
of	O
the	O
addition	O
is	O
written	O
and	O
read	O
.	O
</s>
<s>
In	O
some	O
cases	O
all	O
stalls	O
from	O
such	O
read-after-write	O
data	O
hazards	O
can	O
be	O
completely	O
eliminated	O
by	O
operand	B-General_Concept
forwarding	I-General_Concept
:	O
</s>
<s>
The	O
CPU	B-Device
control	B-General_Concept
unit	I-General_Concept
must	O
implement	O
logic	O
to	O
detect	O
dependencies	O
where	O
operand	B-General_Concept
forwarding	I-General_Concept
makes	O
sense	O
.	O
</s>
<s>
A	O
multiplexer	B-Protocol
can	O
then	O
be	O
used	O
to	O
select	O
the	O
proper	O
register	B-General_Concept
or	O
flip-flop	B-General_Concept
to	O
read	O
the	O
operand	O
from	O
.	O
</s>
