<s>
In	O
order	O
to	O
compete	O
with	O
Intel	O
's	O
Advanced	B-Device
Programmable	I-Device
Interrupt	I-Device
Controller	I-Device
(	O
APIC	O
)	O
,	O
which	O
had	O
enabled	O
the	O
first	O
Intel	O
486-based	O
multiprocessor	B-Operating_System
systems	O
,	O
in	O
early	O
1995	O
AMD	O
and	O
Cyrix	O
proposed	O
as	O
somewhat	O
similar-in-purpose	O
OpenPIC	B-Device
architecture	O
supporting	O
up	O
to	O
32	O
processors	O
.	O
</s>
<s>
The	O
OpenPIC	B-Device
architecture	O
had	O
at	O
least	O
declarative	O
support	O
from	O
IBM	O
and	O
Compaq	O
around	O
1995	O
.	O
</s>
<s>
No	O
x86	O
motherboard	O
was	O
released	O
with	O
OpenPIC	B-Device
however	O
.	O
</s>
<s>
After	O
the	O
OpenPIC	B-Device
's	O
failure	O
in	O
the	O
x86	O
market	O
,	O
AMD	O
licensed	O
the	O
Intel	B-Device
APIC	I-Device
Architecture	I-Device
for	O
its	O
AMD	B-Architecture
Athlon	I-Architecture
and	O
later	O
processors	O
.	O
</s>
<s>
IBM	O
however	O
developed	O
their	O
Multiprocessor	B-Device
Interrupt	I-Device
Controller	I-Device
(	O
MPIC	O
)	O
based	O
on	O
the	O
OpenPIC	B-Device
register	O
specification	O
.	O
</s>
<s>
In	O
the	O
reference	O
IBM	O
design	O
,	O
the	O
processors	O
share	O
the	O
MPIC	O
over	O
a	O
DCR	B-Architecture
bus	I-Architecture
,	O
with	O
their	O
access	O
to	O
the	O
bus	O
controlled	O
by	O
a	O
DCR	O
Arbiter	O
.	O
</s>
<s>
Through	O
various	O
implementations	O
,	O
the	O
MPIC	O
was	O
included	O
in	O
PowerPC	B-Architecture
reference	O
designs	O
and	O
some	O
retail	O
computers	O
.	O
</s>
<s>
IBM	O
used	O
a	O
MPIC	O
based	O
on	O
OpenPIC	B-Device
1.0	O
in	O
their	O
RS/6000	B-Device
F50	O
and	O
one	O
based	O
on	O
OpenPIC	B-Device
1.2	O
in	O
their	O
RS/6000	B-Device
S70	O
.	O
</s>
<s>
Both	O
of	O
these	O
systems	O
also	O
used	O
a	O
dual	O
8259	B-Device
on	O
their	O
PCI-ISA	O
bridges	O
.	O
</s>
<s>
An	O
IBM	O
MPIC	O
was	O
also	O
used	O
in	O
the	O
RS/6000	B-Device
7046	O
Model	O
B50	O
.	O
</s>
<s>
The	O
Apple	O
Hydra	O
Mac	O
I/O	O
(	O
MIO	O
)	O
chip	O
(	O
from	O
the	O
1990s	O
classic	B-Application
Mac	I-Application
OS	I-Application
era	O
)	O
implemented	O
a	O
MPIC	O
alongside	O
a	O
SCSI	B-Architecture
controller	O
,	O
ADB	B-Device
controller	O
,	O
GeoPort	B-Device
controller	O
,	O
and	O
timers	O
.	O
</s>
<s>
The	O
Apple	O
implementation	O
of	O
"	O
Open	O
PIC	O
"	O
(	O
as	O
the	O
Apple	O
documentation	O
of	O
this	O
era	O
spells	O
it	O
)	O
in	O
their	O
first	O
MIO	O
chip	O
for	O
the	O
Common	B-Device
Hardware	I-Device
Reference	I-Device
Platform	I-Device
was	O
based	O
on	O
version	O
1.2	O
of	O
the	O
register	O
specification	O
and	O
supported	O
up	O
to	O
two	O
processors	O
and	O
up	O
to	O
20	O
interrupt	O
sources	O
.	O
</s>
<s>
A	O
MPIC	O
was	O
also	O
incorporated	O
in	O
the	O
newer	O
K2	O
I/O	O
controller	O
used	O
in	O
the	O
Power	B-Device
Mac	I-Device
G5s	I-Device
.	O
</s>
<s>
Freescale	O
also	O
uses	O
a	O
MPIC	O
(	O
"	O
compatible	O
with	O
the	O
Open	O
PIC	O
"	O
)	O
on	O
all	O
its	O
PowerQUICC	B-General_Concept
and	O
QorIQ	B-General_Concept
processors	O
.	O
</s>
<s>
The	O
Linux	O
Kernel-based	B-Application
Virtual	I-Application
Machine	I-Application
(	O
KVM	O
)	O
supports	O
a	O
virtualized	O
MPIC	O
with	O
up	O
to	O
256	O
interrupts	O
,	O
based	O
on	O
the	O
Freescale	O
variants	O
.	O
</s>
