<s>
An	O
Omega	B-Architecture
network	I-Architecture
is	O
a	O
network	B-Architecture
configuration	I-Architecture
often	O
used	O
in	O
parallel	B-Operating_System
computing	I-Operating_System
architectures	B-General_Concept
.	O
</s>
<s>
An	O
8x8	O
Omega	B-Architecture
network	I-Architecture
is	O
a	O
multistage	O
interconnection	O
network	O
,	O
meaning	O
that	O
processing	O
elements	O
(	O
PEs	O
)	O
are	O
connected	O
using	O
multiple	O
stages	O
of	O
switches	O
.	O
</s>
<s>
For	O
N	O
processing	O
element	O
,	O
an	O
Omega	B-Architecture
network	I-Architecture
contains	O
N/2	O
switches	O
at	O
each	O
stage	O
,	O
and	O
log2N	O
stages	O
.	O
</s>
<s>
The	O
Omega	B-Architecture
Network	I-Architecture
is	O
highly	O
blocking	O
,	O
though	O
one	O
path	O
can	O
always	O
be	O
made	O
from	O
any	O
input	O
to	O
any	O
output	O
in	O
a	O
free	O
network	O
.	O
</s>
<s>
In	O
multiprocessing	O
,	O
omega	B-Architecture
networks	I-Architecture
may	O
be	O
used	O
as	O
connectors	O
between	O
the	O
CPUs	B-General_Concept
and	O
their	O
shared	O
memory	O
,	O
in	O
order	O
to	O
decrease	O
the	O
probability	O
that	O
the	O
CPU-to-memory	O
connection	O
becomes	O
a	O
bottleneck	O
.	O
</s>
