<s>
nvSRAM	B-Architecture
is	O
a	O
type	O
of	O
non-volatile	B-General_Concept
random-access	I-General_Concept
memory	I-General_Concept
(	O
NVRAM	B-General_Concept
)	O
.	O
</s>
<s>
nvSRAM	B-Architecture
extends	O
the	O
functionality	O
of	O
basic	O
SRAM	B-Architecture
by	O
adding	O
non-volatile	B-General_Concept
storage	I-General_Concept
such	O
as	O
an	O
EEPROM	B-General_Concept
to	O
the	O
SRAM	B-Architecture
chip	O
.	O
</s>
<s>
In	O
operation	O
,	O
data	O
is	O
written	O
to	O
and	O
read	O
from	O
the	O
SRAM	B-Architecture
portion	O
with	O
high-speed	O
access	O
;	O
the	O
data	O
in	O
SRAM	B-Architecture
can	O
then	O
be	O
stored	O
into	O
or	O
retrieved	O
from	O
the	O
non-volatile	B-General_Concept
storage	I-General_Concept
at	O
lower	O
speeds	O
when	O
needed	O
.	O
</s>
<s>
nvSRAM	B-Architecture
is	O
one	O
of	O
the	O
advanced	O
NVRAM	B-General_Concept
technologies	O
that	O
are	O
fast	O
replacing	O
the	O
battery-backed	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
(	O
BBSRAM	O
)	O
,	O
especially	O
for	O
applications	O
that	O
need	O
battery-free	O
solutions	O
and	O
long-term	O
retention	O
at	O
SRAM	B-Architecture
speeds	O
.	O
</s>
<s>
nvSRAMs	B-Architecture
are	O
used	O
in	O
a	O
wide	O
range	O
of	O
situations	O
:	O
networking	O
,	O
aerospace	O
,	O
and	O
medical	O
,	O
among	O
many	O
others	O
where	O
the	O
preservation	O
of	O
data	O
is	O
critical	O
and	O
where	O
batteries	O
are	O
impractical	O
.	O
</s>
<s>
nvSRAM	B-Architecture
is	O
faster	O
than	O
EPROM	O
and	O
EEPROM	B-General_Concept
solutions	O
.	O
</s>
<s>
When	O
reading	O
and	O
writing	O
data	O
,	O
a	O
nvSRAM	B-Architecture
acts	O
no	O
differently	O
than	O
a	O
standard	O
asynchronous	O
SRAM	B-Architecture
.	O
</s>
<s>
The	O
attached	O
processor	O
or	O
controller	O
sees	O
an	O
8-bit	O
SRAM	B-Architecture
interface	O
and	O
nothing	O
else	O
.	O
</s>
<s>
The	O
STORE	O
operation	O
stores	O
data	O
that	O
is	O
in	O
an	O
SRAM	B-Architecture
array	O
in	O
the	O
non-volatile	B-General_Concept
part	O
.	O
</s>
<s>
Cypress	O
and	O
Simtek	O
nvSRAM	B-Architecture
have	O
three	O
ways	O
to	O
store	O
data	O
in	O
the	O
non-volatile	B-General_Concept
area	O
.	O
</s>
<s>
The	O
capacitor	O
will	O
power	O
the	O
chip	O
long	O
enough	O
to	O
store	O
the	O
SRAM	B-Architecture
contents	O
into	O
the	O
non-volatile	B-General_Concept
part	O
.	O
</s>
<s>
The	O
HSB	O
(	O
Hardware	O
Store	O
Busy	O
)	O
pin	O
externally	O
initiates	O
a	O
non-volatile	B-General_Concept
hardware	O
store	O
operation	O
.	O
</s>
<s>
Using	O
the	O
HSB	O
signal	O
,	O
which	O
requests	O
a	O
non-volatile	B-General_Concept
hardware	O
STORE	O
cycle	O
,	O
is	O
optional	O
.	O
</s>
<s>
SONOS	B-Algorithm
is	O
a	O
cross-sectional	O
structure	O
of	O
MOSFET	B-Architecture
used	O
in	O
Non-volatile	B-General_Concept
memory	I-General_Concept
such	O
as	O
EEPROM	B-General_Concept
and	O
flash	B-Device
memories	I-Device
.	O
</s>
<s>
nvSRAM	B-Architecture
built	O
with	O
SONOS	B-Algorithm
technology	O
is	O
the	O
combination	O
of	O
SRAM	B-Architecture
and	O
EEPROM	B-General_Concept
.	O
</s>
<s>
The	O
SRAM	B-Architecture
cells	O
are	O
paired	O
one	O
to	O
one	O
with	O
EEPROM	B-General_Concept
cells	O
.	O
</s>
<s>
The	O
nvSRAMs	B-Architecture
are	O
in	O
the	O
CMOS	O
process	O
,	O
with	O
the	O
EEPROM	B-General_Concept
cells	O
having	O
a	O
SONOS	B-Algorithm
stack	O
to	O
provide	O
nonvolatile	O
storage	O
.	O
</s>
<s>
nvSRAM	B-Architecture
combines	O
the	O
standard	O
SRAM	B-Architecture
cells	O
with	O
EEPROM	B-General_Concept
cells	O
in	O
SONOS	B-Algorithm
technology	O
to	O
provide	O
a	O
fast	O
read/write	O
access	O
and	O
20	O
years	O
of	O
data	O
retention	O
without	O
power	O
.	O
</s>
<s>
The	O
SRAM	B-Architecture
cells	O
are	O
paired	O
one-to-one	O
with	O
EEPROM	B-General_Concept
cells	O
.	O
</s>
<s>
The	O
nvSRAMs	B-Architecture
are	O
in	O
the	O
CMOS	O
process	O
,	O
with	O
the	O
EEPROM	B-General_Concept
cells	O
having	O
a	O
SONOS	B-Algorithm
stack	O
to	O
provide	O
nonvolatile	O
storage	O
.	O
</s>
<s>
When	O
normal	O
power	O
is	O
applied	O
,	O
the	O
device	O
looks	O
and	O
behaves	O
in	O
a	O
similar	O
manner	O
as	O
a	O
standard	O
SRAM	B-Architecture
.	O
</s>
<s>
However	O
,	O
when	O
power	O
drops	O
out	O
,	O
each	O
cell	O
’s	O
contents	O
can	O
be	O
stored	O
automatically	O
in	O
the	O
nonvolatile	O
element	O
positioned	O
above	O
the	O
SRAM	B-Architecture
cell	O
.	O
</s>
<s>
The	O
SONOS	B-Algorithm
memory	O
uses	O
an	O
insulating	O
layer	O
such	O
as	O
silicon	O
nitride	O
with	O
traps	O
as	O
the	O
charge	O
storage	O
layer	O
.	O
</s>
<s>
In	O
SONOS	B-Algorithm
,	O
the	O
Oxide-Nitride-Oxide(ONO )	O
stack	O
is	O
engineered	O
to	O
maximize	O
the	O
charge-trapping	O
efficiency	O
during	O
erase	O
and	O
program	O
operations	O
and	O
minimize	O
the	O
charge	O
loss	O
during	O
the	O
retention	O
by	O
controlling	O
the	O
deposition	O
parameters	O
in	O
the	O
ONO	O
formation	O
.	O
</s>
<s>
Advantages	O
of	O
SONOS	B-Algorithm
technology	O
:	O
</s>
<s>
nvSRAM	B-Architecture
BBSRAM	O
Ferroelectric	O
RAM	O
Magnetoresistive	B-General_Concept
random-access	I-General_Concept
memory	I-General_Concept
Technique	O
Has	O
non-volatile	B-General_Concept
elements	O
along	O
with	O
high	O
performance	O
SRAM	B-Architecture
Has	O
a	O
lithium	B-Algorithm
energy	O
source	O
for	O
power	O
when	O
external	O
power	O
is	O
off	O
Has	O
a	O
ferroelectric	O
crystal	O
between	O
two	O
electrodes	O
to	O
form	O
a	O
capacitor	O
.	O
</s>
<s>
This	O
effect	O
is	O
used	O
to	O
store	O
data	O
Data	O
retention	O
20	O
yrs	O
7	O
yrs	O
,	O
dependent	O
on	O
battery	O
and	O
ambient	O
temperature	O
10	O
yrs	O
20	O
yrs	O
Endurance	O
Unlimited	O
Limited	O
1010	O
to	O
1014	O
https://www.fujitsu.com/us/Images/MB85R4001A-DS501-00005-3v0-E.pdf	O
http://www.cypress.com/file/136476/download	O
108	O
Store	O
mechanism	O
Autostore	O
initiated	O
when	O
VCC	O
power	O
down	O
is	O
detected	O
Chip	O
enable	O
must	O
be	O
maintained	O
at	O
high	O
logic	O
to	O
prevent	O
inadvertent	O
read/writes	B-General_Concept
Static	O
operation	O
.	O
</s>
