<s>
Numerical	B-Device
Wind	I-Device
Tunnel	I-Device
( 数値風洞	O
)	O
was	O
an	O
early	O
implementation	O
of	O
the	O
vector	O
parallel	O
architecture	O
developed	O
in	O
a	O
joint	O
project	O
between	O
National	O
Aerospace	O
Laboratory	O
of	O
Japan	O
and	O
Fujitsu	O
.	O
</s>
<s>
It	O
stood	O
out	O
at	O
the	O
top	O
of	O
the	O
TOP500	B-Operating_System
during	O
1993-1996	O
.	O
</s>
<s>
With	O
140	O
cores	O
,	O
the	O
Numerical	B-Device
Wind	I-Device
Tunnel	I-Device
reached	O
a	O
Rmax	O
of	O
124.0	O
GFlop/s	O
and	O
a	O
Rpeak	O
of	O
235.8	O
GFlop/s	O
in	O
November	O
1993	O
.	O
</s>
<s>
It	O
consisted	O
of	O
parallel	O
connected	O
166	O
vector	B-Operating_System
processors	I-Operating_System
with	O
a	O
gate	O
delay	O
as	O
low	O
as	O
60	O
ps	O
in	O
the	O
Ga-As	O
chips	O
.	O
</s>
