<s>
In	O
computing	O
,	O
a	O
northbridge	B-Device
(	O
also	O
host	B-Device
bridge	I-Device
,	O
or	O
memory	B-Device
controller	I-Device
hub	I-Device
)	O
is	O
one	O
of	O
two	O
chips	O
comprising	O
the	O
core	O
logic	O
chipset	B-Device
architecture	O
on	O
a	O
PC	B-Device
motherboard	I-Device
.	O
</s>
<s>
A	O
northbridge	B-Device
is	O
connected	O
directly	O
to	O
a	O
CPU	B-General_Concept
via	O
the	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	O
)	O
to	O
handle	O
high-performance	O
tasks	O
,	O
and	O
is	O
usually	O
used	O
in	O
conjunction	O
with	O
a	O
slower	O
southbridge	B-Device
to	O
manage	O
communication	O
between	O
the	O
CPU	B-General_Concept
and	O
other	O
parts	O
of	O
the	O
motherboard	B-Device
.	O
</s>
<s>
Since	O
the	O
2010s	O
,	O
die	O
shrink	O
and	O
improved	O
transistor	O
density	O
have	O
allowed	O
for	O
increasing	O
chipset	B-Device
integration	O
,	O
and	O
the	O
functions	O
performed	O
by	O
northbridges	B-Device
are	O
now	O
often	O
incorporated	O
into	O
other	O
components	O
(	O
like	O
southbridges	B-Device
or	O
CPUs	B-Device
themselves	O
)	O
.	O
</s>
<s>
As	O
of	O
2019	O
,	O
Intel	O
and	O
AMD	O
had	O
both	O
released	O
chipsets	B-Device
in	O
which	O
all	O
northbridge	B-Device
functions	O
had	O
been	O
integrated	O
into	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
Modern	O
Intel	O
Core	O
processors	O
have	O
the	O
northbridge	B-Device
integrated	O
on	O
the	O
CPU	B-General_Concept
die	O
,	O
where	O
it	O
is	O
known	O
as	O
the	O
uncore	B-General_Concept
or	I-General_Concept
system	I-General_Concept
agent	I-General_Concept
.	O
</s>
<s>
On	O
older	O
Intel	O
based	O
PCs	B-Device
,	O
the	O
northbridge	B-Device
was	O
also	O
named	O
external	O
memory	B-Device
controller	I-Device
hub	I-Device
(	O
MCH	O
)	O
or	O
graphics	O
and	O
memory	B-Device
controller	I-Device
hub	I-Device
(	O
GMCH	O
)	O
if	O
equipped	O
with	O
integrated	O
graphics	O
.	O
</s>
<s>
Increasingly	O
these	O
functions	O
became	O
integrated	O
into	O
the	O
CPU	B-General_Concept
chip	O
itself	O
,	O
beginning	O
with	O
memory	O
and	O
graphics	O
controllers	O
.	O
</s>
<s>
For	O
Intel	B-Device
Sandy	I-Device
Bridge	I-Device
and	O
AMD	B-Architecture
Accelerated	I-Architecture
Processing	I-Architecture
Unit	I-Architecture
processors	O
introduced	O
in	O
2011	O
,	O
all	O
of	O
the	O
functions	O
of	O
the	O
northbridge	B-Device
reside	O
on	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
The	O
corresponding	O
southbridge	B-Device
was	O
renamed	O
by	O
Intel	O
as	O
the	O
Platform	B-Device
Controller	I-Device
Hub	I-Device
and	O
by	O
AMD	O
as	O
the	O
Fusion	O
controller	O
hub	O
.	O
</s>
<s>
AMD	O
FX	O
CPUs	B-Device
continued	O
to	O
require	O
external	O
northbridge	B-Device
and	O
southbridge	B-Device
chips	O
.	O
</s>
<s>
Historically	O
,	O
separation	O
of	O
functions	O
between	O
CPU	B-General_Concept
,	O
northbridge	B-Device
,	O
and	O
southbridge	B-Device
chips	O
was	O
necessary	O
due	O
to	O
the	O
difficulty	O
of	O
integrating	O
all	O
components	O
onto	O
a	O
single	O
chip	O
die	O
.	O
</s>
<s>
However	O
,	O
as	O
CPU	B-General_Concept
speeds	O
increased	O
over	O
time	O
,	O
a	O
bottleneck	O
emerged	O
due	O
to	O
limitations	O
caused	O
by	O
data	O
transmission	O
between	O
the	O
CPU	B-General_Concept
and	O
its	O
support	O
chipset	B-Device
.	O
</s>
<s>
The	O
trend	O
for	O
integrated	O
northbridges	B-Device
began	O
near	O
the	O
end	O
of	O
the	O
2000s	O
—	O
for	O
example	O
,	O
the	O
Nvidia	O
GeForce	O
320M	O
GPU	B-Architecture
in	O
the	O
2010	O
MacBook	O
Air	O
was	O
a	O
northbridge/southbridge/GPU	O
combo	O
chip	O
.	O
</s>
<s>
The	O
northbridge	B-Device
typically	O
handles	O
communications	O
among	O
the	O
CPU	B-General_Concept
,	O
in	O
some	O
cases	O
RAM	B-Architecture
,	O
and	O
PCI	O
Express	O
(	O
or	O
AGP	B-Architecture
)	O
video	O
cards	O
,	O
and	O
the	O
southbridge	B-Device
.	O
</s>
<s>
Some	O
northbridges	B-Device
also	O
contain	O
integrated	O
video	O
controllers	O
,	O
also	O
known	O
as	O
a	O
Graphics	O
and	O
Memory	B-Device
Controller	I-Device
Hub	I-Device
(	O
GMCH	O
)	O
in	O
Intel	O
systems	O
.	O
</s>
<s>
Because	O
different	O
processors	O
and	O
RAM	B-Architecture
require	O
different	O
signaling	O
,	O
a	O
given	O
northbridge	B-Device
will	O
typically	O
work	O
with	O
only	O
one	O
or	O
two	O
classes	O
of	O
CPUs	B-Device
and	O
generally	O
only	O
one	O
type	O
of	O
RAM	B-Architecture
.	O
</s>
<s>
There	O
are	O
a	O
few	O
chipsets	B-Device
that	O
support	O
two	O
types	O
of	O
RAM	B-Architecture
;	O
generally	O
,	O
these	O
are	O
made	O
available	O
when	O
there	O
is	O
a	O
shift	O
to	O
a	O
new	O
standard	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
northbridge	B-Device
from	O
the	O
2002	O
Nvidia	O
nForce2	B-Device
chipset	B-Device
only	O
worked	O
with	O
Socket	O
A	O
processors	O
combined	O
with	O
DDR	O
SDRAM	O
.	O
</s>
<s>
The	O
CPU	B-General_Concept
would	O
be	O
at	O
the	O
top	O
of	O
the	O
map	O
comparable	O
to	O
due	O
north	O
on	O
most	O
general	O
purpose	O
geographical	O
maps	O
.	O
</s>
<s>
The	O
CPU	B-General_Concept
would	O
be	O
connected	O
to	O
the	O
chipset	B-Device
via	O
a	O
fast	O
bridge	O
(	O
the	O
northbridge	B-Device
)	O
located	O
north	O
of	O
other	O
system	O
devices	O
as	O
drawn	O
.	O
</s>
<s>
The	O
northbridge	B-Device
would	O
then	O
be	O
connected	O
to	O
the	O
rest	O
of	O
the	O
chipset	B-Device
via	O
a	O
slow	O
bridge	O
(	O
the	O
southbridge	B-Device
)	O
located	O
south	O
of	O
other	O
system	O
devices	O
as	O
drawn	O
.	O
</s>
<s>
The	O
northbridge	B-Device
plays	O
an	O
important	O
part	O
in	O
how	O
far	O
a	O
computer	O
can	O
be	O
overclocked	B-Application
,	O
as	O
its	O
frequency	O
is	O
commonly	O
used	O
as	O
a	O
baseline	O
for	O
the	O
CPU	B-General_Concept
to	O
establish	O
its	O
own	O
operating	O
frequency	O
.	O
</s>
<s>
There	O
is	O
a	O
limit	O
to	O
CPU	B-General_Concept
overclocking	B-Application
,	O
as	O
digital	O
circuits	O
are	O
limited	O
by	O
physical	O
factors	O
such	O
as	O
rise	O
,	O
fall	O
,	O
delay	O
and	O
storage	O
times	O
of	O
the	O
transistors	O
,	O
current	O
gain	O
bandwidth	O
product	O
,	O
parasitic	O
capacitance	O
,	O
and	O
propagation	O
delay	O
,	O
which	O
increases	O
with	O
(	O
among	O
other	O
factors	O
)	O
operating	O
temperature	O
;	O
consequently	O
most	O
overclocking	B-Application
applications	O
have	O
software-imposed	O
limits	O
on	O
the	O
multiplier	O
and	O
external	O
clock	O
setting	O
.	O
</s>
<s>
Additionally	O
,	O
heat	O
is	O
a	O
major	O
limiting	O
factor	O
,	O
as	O
higher	O
voltages	O
are	O
needed	O
to	O
properly	O
activate	O
field	O
effect	O
transistors	O
inside	O
CPUs	B-Device
and	O
this	O
higher	O
voltage	O
produces	O
larger	O
amounts	O
of	O
heat	O
,	O
requiring	O
greater	O
thermal	O
solutions	O
on	O
the	O
die	O
.	O
</s>
<s>
The	O
overall	O
trend	O
in	O
processor	O
design	O
has	O
been	O
to	O
integrate	O
more	O
functions	O
onto	O
fewer	O
components	O
,	O
which	O
decreases	O
overall	O
motherboard	B-Device
cost	O
and	O
improves	O
performance	O
.	O
</s>
<s>
The	O
memory	B-General_Concept
controller	I-General_Concept
,	O
which	O
handles	O
communication	O
between	O
the	O
CPU	B-General_Concept
and	O
RAM	B-Architecture
,	O
was	O
moved	O
onto	O
the	O
processor	O
die	O
by	O
AMD	O
beginning	O
with	O
their	O
AMD	B-Device
K8	I-Device
processors	O
and	O
by	O
Intel	O
with	O
their	O
Nehalem	B-Device
processors	O
.	O
</s>
<s>
One	O
of	O
the	O
advantages	O
of	O
having	O
the	O
memory	B-General_Concept
controller	I-General_Concept
integrated	O
on	O
the	O
CPU	B-General_Concept
die	O
is	O
to	O
reduce	O
latency	O
from	O
the	O
CPU	B-General_Concept
to	O
memory	O
.	O
</s>
<s>
Another	O
example	O
of	O
this	O
kind	O
of	O
change	O
is	O
Nvidia	O
's	O
nForce3	B-Device
for	O
AMD	B-Device
K8	I-Device
systems	O
.	O
</s>
<s>
It	O
combines	O
all	O
of	O
the	O
features	O
of	O
a	O
normal	O
southbridge	B-Device
with	O
an	O
Accelerated	B-Architecture
Graphics	I-Architecture
Port	I-Architecture
(	O
AGP	B-Architecture
)	O
port	O
and	O
connects	O
directly	O
to	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
On	O
nForce4	B-Device
boards	O
it	O
was	O
marketed	O
as	O
a	O
media	O
communications	O
processor	O
(	O
MCP	O
)	O
.	O
</s>
<s>
AMD	B-Architecture
Accelerated	I-Architecture
Processing	I-Architecture
Unit	I-Architecture
processors	O
feature	O
full	O
integration	O
of	O
northbridge	B-Device
functions	O
onto	O
the	O
CPU	B-General_Concept
chip	O
,	O
along	O
with	O
processor	O
cores	O
,	O
memory	B-General_Concept
controller	I-General_Concept
,	O
high	O
speed	O
PCI	O
Express	O
interface	O
(	O
usually	O
for	O
graphics	O
card	O
)	O
,	O
and	O
integrated	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
(	O
iGPU	O
)	O
.	O
</s>
<s>
This	O
was	O
an	O
evolution	O
of	O
the	O
AMD	B-Device
K8	I-Device
,	O
since	O
the	O
memory	B-General_Concept
controller	I-General_Concept
was	O
integrated	O
on	O
the	O
CPU	B-General_Concept
die	O
in	O
the	O
AMD64	O
.	O
</s>
<s>
The	O
northbridge	B-Device
was	O
replaced	O
by	O
the	O
system	B-General_Concept
agent	I-General_Concept
introduced	O
by	O
the	O
Intel	B-Device
Sandy	I-Device
Bridge	I-Device
microarchitecture	B-General_Concept
in	O
2011	O
,	O
which	O
essentially	O
handles	O
all	O
previous	O
Northbridge	B-Device
functions	O
.	O
</s>
<s>
Intel	O
's	O
Sandy	B-Device
Bridge	I-Device
processors	O
feature	O
full	O
integration	O
of	O
northbridge	B-Device
functions	O
onto	O
the	O
CPU	B-General_Concept
chip	O
,	O
along	O
with	O
processor	O
cores	O
,	O
memory	B-General_Concept
controller	I-General_Concept
,	O
high	O
speed	O
PCI	O
Express	O
interface	O
and	O
integrated	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
(	O
GPU	B-Architecture
)	O
.	O
</s>
<s>
This	O
was	O
a	O
further	O
evolution	O
of	O
the	O
Westmere	O
architecture	O
,	O
which	O
also	O
featured	O
a	O
CPU	B-General_Concept
and	O
GPU	B-Architecture
in	B-Algorithm
the	I-Algorithm
same	I-Algorithm
package	I-Algorithm
.	O
</s>
<s>
Recent	O
AMD	O
processors	O
starting	O
with	O
the	O
Zen	O
2	O
have	O
moved	O
some	O
I/O	O
functions	O
out	O
of	O
the	O
CPU	B-General_Concept
die	O
onto	O
an	O
I/O	O
die	O
on	O
the	O
same	O
MCM	B-Algorithm
package	O
as	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
This	O
die	O
is	O
not	O
normally	O
considered	O
to	O
be	O
part	O
of	O
the	O
Northbridge	B-Device
,	O
since	O
it	O
's	O
in	B-Algorithm
the	I-Algorithm
same	I-Algorithm
package	I-Algorithm
as	O
the	O
CPU	B-General_Concept
,	O
but	O
it	O
serves	O
some	O
of	O
the	O
same	O
functions	O
.	O
</s>
