<s>
The	O
Nord-100	B-Device
was	O
a	O
16-bit	B-Device
minicomputer	B-Architecture
series	O
made	O
by	O
Norsk	O
Data	O
,	O
introduced	O
in	O
1979	O
.	O
</s>
<s>
It	O
shipped	O
with	O
the	O
Sintran	B-Operating_System
III	I-Operating_System
operating	B-General_Concept
system	I-General_Concept
,	O
and	O
the	O
architecture	O
was	O
based	O
on	O
,	O
and	O
backward	O
compatible	O
with	O
,	O
the	O
Nord-10	B-Device
line	O
.	O
</s>
<s>
The	O
Nord-100	B-Device
was	O
originally	O
named	O
the	O
Nord-10/M	O
(	O
M	O
for	O
Micro	O
)	O
as	O
a	O
bit	B-General_Concept
sliced	I-General_Concept
OEM	O
processor	O
.	O
</s>
<s>
The	O
board	O
was	O
laid	O
out	O
,	O
finished	O
,	O
and	O
tested	O
when	O
they	O
realized	O
that	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
was	O
far	O
faster	O
than	O
the	O
Nord-10/S	B-Device
.	O
</s>
<s>
The	O
result	O
was	O
that	O
all	O
the	O
marketing	O
material	O
for	O
the	O
new	O
NORD-10/M	O
was	O
discarded	O
,	O
the	O
board	O
was	O
rechristened	O
the	O
Nord-100	B-Device
,	O
and	O
extensively	O
advertised	O
as	O
the	O
successor	O
of	O
the	O
Nord-10	B-Device
line	O
.	O
</s>
<s>
Later	O
,	O
in	O
an	O
effort	O
to	O
internationalize	O
their	O
line	O
,	O
the	O
machine	O
was	O
renamed	O
ND-100	B-Device
.	O
</s>
<s>
The	O
ND-100	B-Device
line	O
used	O
a	O
custom	O
processor	O
,	O
and	O
like	O
the	O
PDP-11	B-Device
line	O
,	O
the	O
CPU	O
decided	O
the	O
name	O
of	O
the	O
computer	O
.	O
</s>
<s>
The	O
ND-100	B-Device
line	O
was	O
machine-instruction	O
compatible	O
with	O
the	O
Nord-10	B-Device
line	O
,	O
except	O
for	O
some	O
extended	O
instructions	O
,	O
all	O
in	O
supervisor	O
mode	O
,	O
mostly	O
used	O
by	O
the	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
Like	O
most	O
processors	O
of	O
its	O
time	O
,	O
the	O
native	O
bit	O
grouping	O
was	O
octal	O
,	O
despite	O
the	O
16-bit	B-Device
word	O
length	O
.	O
</s>
<s>
The	O
ND-100	B-Device
series	O
had	O
a	O
microcoded	B-Device
CPU	O
,	O
with	O
downloadable	O
microcode	B-Device
,	O
and	O
was	O
considered	O
a	O
complex	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
CISC	O
)	O
processor	O
.	O
</s>
<s>
The	O
ND-100	B-Device
was	O
implemented	O
using	O
medium-scale	O
integration	O
(	O
MSI	O
)	O
logic	O
and	O
bit-slice	B-General_Concept
processors	I-General_Concept
.	O
</s>
<s>
The	O
ND-100	B-Device
was	O
frequently	O
sold	O
together	O
with	O
a	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
card	O
,	O
the	O
MMS	O
.	O
</s>
<s>
Slot	O
1	O
was	O
reserved	O
for	O
the	O
Tracer	O
,	O
a	O
hardware	O
debugger	B-Application
system	O
.	O
</s>
<s>
The	O
processor	O
was	O
upgraded	O
by	O
replacing	O
the	O
microcode	B-Device
PROM	O
.	O
</s>
<s>
The	O
ND-110	O
was	O
an	O
incremental	O
improvement	O
over	O
the	O
ND-100	B-Device
.	O
</s>
<s>
The	O
Arithmetical	B-General_Concept
and	I-General_Concept
Logical	I-General_Concept
Unit	I-General_Concept
gate	O
array	O
(	O
ALU	B-General_Concept
,	O
also	O
known	O
as	O
the	O
BUFALU	O
)	O
.	O
</s>
<s>
Replaced	O
four	O
Am2901	B-General_Concept
bit-slice	B-General_Concept
processors	I-General_Concept
,	O
and	O
some	O
added	O
registers	O
like	O
the	O
data	O
bus	O
register	O
the	O
general	O
purpose	O
register	O
,	O
and	O
the	O
internal	O
register	O
block	O
.	O
</s>
<s>
It	O
implemented	O
hardware	O
address	O
arithmetic	O
,	O
which	O
in	O
the	O
ND-100	B-Device
had	O
been	O
done	O
in	O
microcode	B-Device
.	O
</s>
<s>
Along	O
with	O
the	O
macro-instruction	O
cache	O
memory	O
also	O
in	O
the	O
ND-100	B-Device
,	O
the	O
ND-110	O
had	O
a	O
unique	O
implementation	O
of	O
cache	O
memory	O
on	O
the	O
micro-instruction	O
level	O
.	O
</s>
<s>
The	O
step	O
termed	O
mapping	O
in	O
the	O
ND-100	B-Device
was	O
then	O
avoided	O
because	O
the	O
first	O
micro-instruction	O
word	O
of	O
a	O
macro-instruction	O
was	O
written	O
into	O
the	O
control	B-General_Concept
store	I-General_Concept
cache	O
.	O
</s>
<s>
Unlike	O
the	O
ND-100	B-Device
CPU	O
,	O
it	O
handled	O
synchronous	O
interrupts	O
as	O
traps	O
,	O
similar	O
to	O
how	O
it	O
was	O
handled	O
by	O
the	O
ND-500	B-Device
.	O
</s>
<s>
The	O
control	B-General_Concept
store	I-General_Concept
consisted	O
of	O
4K	O
x	O
4	O
bit	O
40ns	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
(	O
SRAM	O
)	O
chips	O
.	O
</s>
<s>
This	O
meant	O
that	O
the	O
control	B-General_Concept
store	I-General_Concept
was	O
writable	O
.	O
</s>
<s>
It	O
was	O
loaded	O
at	O
power	O
up	O
and	O
Master	O
Clear	O
from	O
two	O
32Kx8	O
bit	O
erasable	B-General_Concept
programmable	I-General_Concept
read-only	I-General_Concept
memory	I-General_Concept
(	O
EPROM	B-General_Concept
)	O
units	O
.	O
</s>
<s>
This	O
was	O
the	O
ND-110	O
with	O
the	O
CX	O
microcode	B-Device
programmable	B-General_Concept
read-only	I-General_Concept
memory	I-General_Concept
(	O
PROM	O
)	O
.	O
</s>
<s>
The	O
ND-120	O
CPU	O
was	O
a	O
complete	O
reimplementation	O
on	O
an	O
LSI	O
chip	O
(	O
The	O
so-called	O
Delilah	O
chip	O
)	O
,	O
and	O
was	O
originally	O
intended	O
to	O
be	O
sold	O
as	O
the	O
ND-1000	O
,	O
to	O
reflect	O
the	O
technology	O
change	O
,	O
which	O
paralleled	O
the	O
change	O
from	O
the	O
ND-500	B-Device
series	O
to	O
the	O
ND-5000	B-Device
(	O
codenamed	O
Samson	B-Application
)	O
.	O
</s>
<s>
The	O
Samson/Delilah	O
naming	O
scheme	O
may	O
reflect	O
that	O
around	O
the	O
time	O
of	O
the	O
development	O
of	O
the	O
ND-120	O
,	O
it	O
was	O
increasingly	O
clear	O
that	O
the	O
mixed	O
16/32	O
-bit	O
architecture	O
was	O
a	O
bottleneck	O
for	O
the	O
ND-500(0 )	O
architecture	O
;	O
Internal	O
technical	O
documentation	O
used	O
at	O
Norsk	O
Data	O
for	O
the	O
Delilah	O
chip	O
has	O
a	O
drawing	O
of	O
a	O
grinning	O
woman	O
with	O
hair	O
in	O
her	O
clenched	O
fist	O
.	O
</s>
