<s>
Nios	B-Device
II	I-Device
is	O
a	O
32-bit	O
embedded	O
processor	O
architecture	O
designed	O
specifically	O
for	O
the	O
Altera	O
family	O
of	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
(	O
FPGA	B-Architecture
)	O
integrated	O
circuits	O
.	O
</s>
<s>
Nios	B-Device
II	I-Device
incorporates	O
many	O
enhancements	O
over	O
the	O
original	O
Nios	B-Device
architecture	O
,	O
making	O
it	O
more	O
suitable	O
for	O
a	O
wider	O
range	O
of	O
embedded	O
computing	O
applications	O
,	O
from	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
(	O
DSP	O
)	O
to	O
system-control	O
.	O
</s>
<s>
Nios	B-Device
II	I-Device
is	O
a	O
successor	O
to	O
Altera	O
's	O
first	O
configurable	O
16-bit	B-Device
embedded	O
processor	O
Nios	B-Device
,	O
introduced	O
in	O
2000	O
.	O
</s>
<s>
Like	O
the	O
original	O
Nios	B-Device
,	O
the	O
Nios	B-Device
II	I-Device
architecture	O
is	O
a	O
RISC	B-Architecture
soft-core	B-Device
architecture	O
which	O
is	O
implemented	O
entirely	O
in	O
the	O
programmable	O
logic	O
and	O
memory	O
blocks	O
of	O
Altera	O
FPGAs	B-Architecture
.	O
</s>
<s>
The	O
soft-core	B-Device
nature	O
of	O
the	O
Nios	B-Device
II	I-Device
processor	O
lets	O
the	O
system	O
designer	O
specify	O
and	O
generate	O
a	O
custom	O
Nios	B-Device
II	I-Device
core	O
,	O
tailored	O
for	O
his	O
or	O
her	O
specific	O
application	O
requirements	O
.	O
</s>
<s>
System	O
designers	O
can	O
extend	O
the	O
Nios	B-Device
II	I-Device
's	O
basic	O
functionality	O
by	O
adding	O
a	O
predefined	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
,	O
or	O
defining	O
custom	O
instructions	O
and	O
custom	O
peripherals	O
.	O
</s>
<s>
Similar	O
to	O
native	O
Nios	B-Device
II	I-Device
instructions	O
,	O
user-defined	O
instructions	O
accept	O
values	O
from	O
up	O
to	O
two	O
32-bit	O
source	O
registers	O
and	O
optionally	O
write	O
back	O
a	O
result	O
to	O
a	O
32-bit	O
destination	O
register	O
.	O
</s>
<s>
By	O
using	O
custom	O
instructions	O
,	O
the	O
system	O
designers	O
can	O
fine-tune	O
the	O
system	O
hardware	O
to	O
meet	O
performance	O
goals	O
and	O
also	O
the	O
designer	O
can	O
easily	O
handle	O
the	O
instruction	O
as	O
a	O
macro	O
in	O
C	B-Language
.	O
</s>
<s>
Introduced	O
with	O
Quartus	B-Language
8.0	O
,	O
the	O
optional	O
MMU	B-General_Concept
enables	O
Nios	B-Device
II	I-Device
to	O
run	O
operating	O
systems	O
which	O
require	O
hardware-based	O
paging	O
and	O
protection	O
,	O
such	O
as	O
the	O
Linux	B-Application
kernel	O
.	O
</s>
<s>
Without	O
an	O
MMU	B-General_Concept
,	O
Nios	B-Device
is	O
restricted	O
to	O
operating	O
systems	O
which	O
use	O
a	O
simplified	O
protection	O
and	O
virtual	O
memory-model	O
:	O
e.g.	O
,	O
µClinux	O
and	O
FreeRTOS	B-Operating_System
.	O
</s>
<s>
Introduced	O
with	O
Quartus	B-Language
8.0	O
,	O
the	O
optional	O
MPU	B-General_Concept
provides	O
memory	O
protection	O
similar	O
to	O
that	O
provided	O
by	O
an	O
MMU	B-General_Concept
but	O
with	O
a	O
simpler	O
programming	O
model	O
and	O
without	O
the	O
performance	O
overhead	O
associated	O
with	O
an	O
MMU	B-General_Concept
.	O
</s>
<s>
Nios	B-Device
II	I-Device
classic	O
is	O
offered	O
in	O
3	O
different	O
configurations	O
:	O
Nios	O
II/f	O
(	O
fast	O
)	O
,	O
Nios	O
II/s	O
(	O
standard	O
)	O
,	O
and	O
Nios	O
II/e	O
(	O
economy	O
)	O
.	O
</s>
<s>
Nios	B-Device
II	I-Device
gen2	O
is	O
offered	O
in	O
2	O
different	O
configurations	O
:	O
Nios	O
II/f	O
(	O
fast	O
)	O
,	O
and	O
Nios	O
II/e	O
(	O
economy	O
)	O
.	O
</s>
<s>
This	O
core	O
implementation	O
is	O
not	O
longer	O
supported	O
for	O
Altera	B-Language
Quartus	I-Language
II	O
v.17	O
and	O
newer	O
.	O
</s>
<s>
The	O
Nios	O
II/e	O
core	O
is	O
designed	O
for	O
smallest	O
possible	O
logic	O
utilization	O
of	O
FPGAs	B-Architecture
.	O
</s>
<s>
This	O
is	O
especially	O
efficient	O
for	O
low-cost	O
Cyclone	O
II	O
FPGA	B-Architecture
applications	O
.	O
</s>
<s>
Nios	B-Device
II	I-Device
uses	O
the	O
Avalon	O
switch	B-Architecture
fabric	I-Architecture
as	O
the	O
interface	O
to	O
its	O
embedded	O
peripherals	O
.	O
</s>
<s>
Compared	O
to	O
a	O
traditional	O
bus	O
in	O
a	O
processor-based	O
system	O
,	O
which	O
lets	O
only	O
one	O
bus	O
master	O
access	O
the	O
bus	O
at	O
a	O
time	O
,	O
the	O
Avalon	O
switch	B-Architecture
fabric	I-Architecture
,	O
using	O
a	O
slave-side	O
arbitration	O
scheme	O
,	O
lets	O
multiple	O
masters	O
operate	O
simultaneously	O
.	O
</s>
<s>
Development	O
for	O
Nios	B-Device
II	I-Device
consists	O
of	O
two	O
separate	O
steps	O
:	O
hardware	O
generation	O
and	O
software	O
creation	O
.	O
</s>
<s>
Nios	B-Device
II	I-Device
hardware	O
designers	O
use	O
the	O
Qsys	O
system	O
integration	O
tool	O
,	O
a	O
component	O
of	O
the	O
Quartus-II	O
package	O
,	O
to	O
configure	O
and	O
generate	O
a	O
Nios	B-Device
system	O
.	O
</s>
<s>
The	O
configuration	O
graphical	B-Application
user	I-Application
interface	I-Application
(	O
GUI	B-Application
)	O
allows	O
users	O
to	O
choose	O
the	O
Nios-II	O
'	O
s	O
feature-set	O
,	O
and	O
to	O
add	O
peripheral	O
and	O
I/O	O
-blocks	O
(	O
timers	O
,	O
memory-controllers	O
,	O
serial	O
interface	O
,	O
etc	O
.	O
)	O
</s>
<s>
When	O
the	O
hardware	O
specification	O
is	O
complete	O
,	O
Quartus-II	O
performs	O
the	O
synthesis	O
,	O
place	O
&	O
route	O
to	O
implement	O
the	O
entire	O
system	O
on	O
the	O
selected	O
FPGA	B-Architecture
target	O
.	O
</s>
<s>
Qsys	O
is	O
replacing	O
the	O
older	O
SOPC	O
(	O
System-on-a-Programmable-Chip	O
)	O
Builder	O
,	O
which	O
could	O
also	O
be	O
used	O
to	O
build	O
a	O
Nios	B-Device
II	I-Device
system	O
,	O
and	O
is	O
being	O
recommended	O
for	O
new	O
projects	O
.	O
</s>
<s>
Based	O
on	O
the	O
Eclipse	B-Application
IDE	I-Application
,	O
the	O
EDS	O
includes	O
a	O
C/C	O
++	O
compiler	O
(	O
based	O
on	O
the	O
GNU	B-Application
toolchain	I-Application
)	O
,	O
debugger	O
,	O
and	O
an	O
instruction-set	O
simulator	O
.	O
</s>
<s>
EDS	O
allows	O
programmers	O
to	O
test	O
their	O
application	O
in	O
simulation	O
,	O
or	O
download	O
and	O
run	O
their	O
compiled	O
application	O
on	O
the	O
actual	O
FPGA	B-Architecture
host	O
.	O
</s>
<s>
Because	O
the	O
C/C	O
++	O
development-chain	O
is	O
based	O
on	O
GCC	O
,	O
the	O
vast	O
majority	O
of	O
open	B-Application
source	I-Application
software	I-Application
for	O
Linux	B-Application
compiles	O
and	O
runs	O
with	O
minimal	O
or	O
no	O
modification	O
.	O
</s>
<s>
Third-party	O
operating-systems	O
have	O
also	O
been	O
ported	O
to	O
Nios	B-Device
II	I-Device
.	O
</s>
<s>
These	O
include	O
Micrium	O
MicroC/OS	B-Operating_System
-II	I-Operating_System
,	O
eCos	B-Operating_System
,	O
Segger	O
Microcontroller	O
embOS	O
,	O
ChibiOS/RT	B-Operating_System
,	O
μCLinux	B-Application
and	O
FreeRTOS	B-Operating_System
.	O
</s>
<s>
Nios	B-Device
II	I-Device
is	O
comparable	O
to	O
MicroBlaze	B-Device
,	O
a	O
competing	O
softcore	B-Device
CPU	I-Device
for	O
the	O
Xilinx	O
family	O
of	O
FPGA	B-Architecture
.	O
</s>
<s>
Unlike	O
MicroBlaze	B-Device
,	O
Nios	B-Device
II	I-Device
is	O
licensable	O
for	O
standard-cell	O
ASICs	O
through	O
a	O
third-party	O
IP	O
provider	O
,	O
Synopsys	O
Designware	O
.	O
</s>
<s>
Through	O
the	O
Designware	O
license	O
,	O
designers	O
can	O
port	O
Nios-based	O
designs	O
from	O
an	O
FPGA-platform	O
to	O
a	O
mass	O
production	O
ASIC-device	O
.	O
</s>
