<s>
NeuroMatrix	B-General_Concept
is	O
a	O
digital	B-Architecture
signal	I-Architecture
processor	I-Architecture
(	O
DSP	O
)	O
series	O
developed	O
by	O
NTC	O
Module	O
.	O
</s>
<s>
The	O
DSP	O
has	O
a	O
VLIW/SIMD	O
architecture	O
.	O
</s>
<s>
It	O
consists	O
of	O
a	O
32-bit	O
RISC	B-Architecture
core	O
and	O
a	O
64-bit	O
vector	O
co-processor	O
.	O
</s>
<s>
6539368	O
B1	O
)	O
and	O
is	O
optimized	O
to	O
support	O
the	O
implementation	O
of	O
artificial	B-Architecture
neural	I-Architecture
networks	I-Architecture
.	O
</s>
<s>
From	O
this	O
derives	O
the	O
name	O
NeuroMatrix	B-General_Concept
Core	O
(	O
NMC	O
)	O
.	O
</s>
<s>
Newer	O
devices	O
contain	O
multiple	O
DSP	O
cores	O
and	O
additional	O
ARM	B-Architecture
or	O
PowerPC	O
470	O
cores	O
.	O
</s>
<s>
—	O
2002	O
?	O
2501501879VM4nm64051x	O
NMC3	O
—	O
2009	O
?	O
1501879VM5Yanm64061x	O
NMC3	O
—	O
2013903201879VM6Yanm64072x	O
NMC4	O
—	O
2016655001879VM8Yanm640816x	O
NMC45x	O
ARM	B-Architecture
Cortex-A52019288001879VYa1Ya2x	O
NMC31x	O
ARM1176JZF-S201390328K1879KhB1Ya1x	O
NMC31x	O
ARM1176JZF-S2011903241879KhK1Ya2x	O
NMC31x	O
ARM1176JZF-S20109081.92K1888VS0182x	O
NMC31x	O
ARM1176JZF-S2016653201888VS0481x	O
ARM	B-Architecture
Cortex-A52019	O
?	O
286001888VS0582x	O
NMC31x	O
ARM	B-Architecture
Cortex-A52020	O
?	O
</s>
