<s>
The	O
NetBurst	B-Device
microarchitecture	O
,	O
called	O
P68	O
inside	O
Intel	O
,	O
was	O
the	O
successor	O
to	O
the	O
P6	B-Device
microarchitecture	I-Device
in	O
the	O
x86	B-Operating_System
family	O
of	O
central	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
(	O
CPUs	O
)	O
made	O
by	O
Intel	O
.	O
</s>
<s>
The	O
first	O
CPU	O
to	O
use	O
this	O
architecture	O
was	O
the	O
Willamette-core	O
Pentium	B-General_Concept
4	I-General_Concept
,	O
released	O
on	O
November	O
20	O
,	O
2000	O
and	O
the	O
first	O
of	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
CPUs	O
;	O
all	O
subsequent	O
Pentium	B-General_Concept
4	I-General_Concept
and	O
Pentium	B-Device
D	I-Device
variants	O
have	O
also	O
been	O
based	O
on	O
NetBurst	B-Device
.	O
</s>
<s>
In	O
mid-2004	O
,	O
Intel	O
released	O
the	O
Foster	O
core	O
,	O
which	O
was	O
also	O
based	O
on	O
NetBurst	B-Device
,	O
thus	O
switching	O
the	O
Xeon	B-Device
CPUs	O
to	O
the	O
new	O
architecture	O
as	O
well	O
.	O
</s>
<s>
Pentium	O
4-based	O
Celeron	B-Device
CPUs	O
also	O
use	O
the	O
NetBurst	B-Device
architecture	O
.	O
</s>
<s>
NetBurst	B-Device
was	O
replaced	O
with	O
the	O
Core	B-Device
microarchitecture	I-Device
based	O
on	O
P6	B-Device
,	O
released	O
in	O
July	O
2006	O
.	O
</s>
<s>
The	O
NetBurst	B-Device
microarchitecture	O
includes	O
features	O
such	O
as	O
Hyper-threading	B-Operating_System
,	O
Hyper	O
Pipelined	O
Technology	O
,	O
Rapid	O
Execution	O
Engine	O
,	O
Execution	O
Trace	O
Cache	O
,	O
and	O
replay	B-Device
system	I-Device
which	O
all	O
were	O
introduced	O
for	O
the	O
first	O
time	O
in	O
this	O
particular	O
microarchitecture	O
,	O
and	O
some	O
never	O
appeared	O
again	O
afterwards	O
.	O
</s>
<s>
Hyper-threading	B-Operating_System
is	O
Intel	O
's	O
proprietary	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
implementation	O
used	O
to	O
improve	O
parallelization	O
of	O
computations	O
(	O
doing	O
multiple	O
tasks	O
at	O
once	O
)	O
performed	O
on	O
x86	B-Operating_System
processors	O
.	O
</s>
<s>
Intel	O
introduced	O
it	O
with	O
NetBurst	B-Device
processors	O
in	O
2002	O
.	O
</s>
<s>
Later	O
Intel	O
reintroduced	O
it	O
in	O
the	O
Nehalem	B-Device
microarchitecture	I-Device
after	O
its	O
absence	O
in	O
the	O
Core	O
2	O
.	O
</s>
<s>
Later	O
revisions	O
of	O
the	O
Northwood	O
core	O
,	O
along	O
with	O
the	O
Prescott	O
core	O
(	O
and	B-Device
derivatives	I-Device
)	O
have	O
an	O
effective	O
800MHz	O
front-side	O
bus	O
(	O
200	O
MHz	O
quad	O
pumped	O
)	O
.	O
</s>
<s>
The	O
Wilamette	O
and	O
Northwood	O
cores	O
contain	O
a	O
20-stage	O
instruction	B-General_Concept
pipeline	I-General_Concept
.	O
</s>
<s>
This	O
is	O
a	O
significant	O
increase	O
in	O
the	O
number	O
of	O
stages	O
compared	O
to	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
,	O
which	O
had	O
only	O
10	O
stages	O
in	O
its	O
pipeline	O
.	O
</s>
<s>
A	O
drawback	O
of	O
longer	O
pipelines	O
is	O
the	O
increase	O
in	O
the	O
number	O
of	O
stages	O
that	O
need	O
to	O
be	O
traced	O
back	O
in	O
the	O
event	O
that	O
the	O
branch	B-General_Concept
misprediction	I-General_Concept
,	O
increasing	O
the	O
penalty	O
of	O
said	O
misprediction	B-General_Concept
.	O
</s>
<s>
To	O
address	O
this	O
issue	O
,	O
Intel	O
devised	O
the	O
Rapid	O
Execution	O
Engine	O
and	O
has	O
invested	O
a	O
great	O
deal	O
into	O
its	O
branch	B-General_Concept
prediction	I-General_Concept
technology	O
,	O
which	O
Intel	O
claims	O
reduces	O
branch	B-General_Concept
mispredictions	I-General_Concept
by	O
33%	O
over	O
Pentium	B-General_Concept
III	I-General_Concept
.	O
</s>
<s>
With	O
this	O
technology	O
,	O
the	O
two	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
(	O
ALUs	O
)	O
in	O
the	O
core	O
of	O
the	O
CPU	O
are	O
double-pumped	O
,	O
meaning	O
that	O
they	O
actually	O
operate	O
at	O
twice	O
the	O
core	O
clock	O
frequency	O
.	O
</s>
<s>
An	O
example	O
is	O
shift	O
and	O
rotate	O
operations	O
,	O
which	O
suffer	O
from	O
the	O
lack	O
of	O
a	O
barrel	O
shifter	O
which	O
was	O
present	O
on	O
every	O
x86	B-Operating_System
CPU	O
beginning	O
with	O
the	O
i386	O
,	O
including	O
the	O
main	O
competitor	O
processor	O
,	O
Athlon	B-Architecture
.	O
</s>
<s>
It	O
stores	O
decoded	O
micro-operations	B-General_Concept
,	O
so	O
that	O
when	O
executing	O
a	O
new	O
instruction	O
,	O
instead	O
of	O
fetching	O
and	O
decoding	O
the	O
instruction	O
again	O
,	O
the	O
CPU	O
directly	O
accesses	O
the	O
decoded	O
micro-ops	B-General_Concept
from	O
the	O
trace	O
cache	O
,	O
thereby	O
saving	O
considerable	O
time	O
.	O
</s>
<s>
Moreover	O
,	O
the	O
micro-ops	B-General_Concept
are	O
cached	O
in	O
their	O
predicted	O
path	O
of	O
execution	O
,	O
which	O
means	O
that	O
when	O
instructions	O
are	O
fetched	O
by	O
the	O
CPU	O
from	O
the	O
cache	O
,	O
they	O
are	O
already	O
present	O
in	O
the	O
correct	O
order	O
of	O
execution	O
.	O
</s>
<s>
Intel	O
later	O
introduced	O
a	O
similar	O
but	O
simpler	O
concept	O
with	O
Sandy	B-Device
Bridge	I-Device
called	O
micro-operation	B-General_Concept
cache	O
(	O
UOP	O
cache	O
)	O
.	O
</s>
<s>
The	O
replay	B-Device
system	I-Device
is	O
a	O
subsystem	O
within	O
the	O
Intel	B-General_Concept
Pentium	I-General_Concept
4	I-General_Concept
processor	O
to	O
catch	O
operations	O
that	O
have	O
been	O
mistakenly	O
sent	O
for	O
execution	O
by	O
the	O
processor	O
's	O
scheduler	O
.	O
</s>
<s>
Operations	O
caught	O
by	O
the	O
replay	B-Device
system	I-Device
are	O
then	O
re-executed	O
in	O
a	O
loop	O
until	O
the	O
conditions	O
necessary	O
for	O
their	O
proper	O
execution	O
have	O
been	O
fulfilled	O
.	O
</s>
<s>
The	O
Intel	B-Device
NetBurst	I-Device
architecture	O
allows	O
branch	B-General_Concept
prediction	I-General_Concept
hints	O
to	O
be	O
inserted	O
into	O
the	O
code	O
to	O
tell	O
whether	O
the	O
static	O
prediction	O
should	O
be	O
taken	O
or	O
not	O
taken	O
,	O
while	O
this	O
feature	O
was	O
abandoned	O
in	O
later	O
Intel	O
processors	O
.	O
</s>
<s>
According	O
to	O
Intel	O
,	O
NetBurst	B-Device
's	O
branch	B-General_Concept
prediction	I-General_Concept
algorithm	O
is	O
33%	O
better	O
than	O
the	O
one	O
in	O
P6	B-Device
.	O
</s>
<s>
Despite	O
these	O
enhancements	O
,	O
the	O
NetBurst	B-Device
architecture	O
created	O
obstacles	O
for	O
engineers	O
trying	O
to	O
scale	O
up	O
its	O
performance	O
.	O
</s>
<s>
Intel	O
abandoned	O
NetBurst	B-Device
in	O
2006	O
after	O
the	O
heat	O
problems	O
became	O
unacceptable	O
and	O
then	O
developed	O
the	O
Core	B-Device
microarchitecture	I-Device
,	O
inspired	O
by	O
the	O
P6	B-Device
Core	O
of	O
the	O
Pentium	B-Device
Pro	I-Device
to	O
the	O
Tualatin	O
Pentium	O
III-S	O
,	O
and	O
most	O
directly	O
the	O
Pentium	B-Architecture
M	I-Architecture
.	O
</s>
<s>
Intel	O
replaced	O
the	O
original	O
Willamette	O
core	O
with	O
a	O
redesigned	O
version	O
of	O
the	O
NetBurst	B-Device
microarchitecture	O
called	O
Northwood	O
in	O
January	O
2002	O
.	O
</s>
<s>
The	O
Northwood	O
design	O
combined	O
an	O
increased	O
cache	O
size	O
,	O
a	O
smaller	O
130nm	B-Algorithm
fabrication	O
process	O
,	O
and	O
Hyper-threading	B-Operating_System
(	O
although	O
initially	O
all	O
models	O
but	O
the	O
3.06GHz	O
model	O
had	O
this	O
feature	O
disabled	O
)	O
to	O
produce	O
a	O
more	O
modern	O
,	O
higher-performing	O
version	O
of	O
the	O
NetBurst	B-Device
microarchitecture	O
.	O
</s>
<s>
The	O
Prescott	O
core	O
was	O
produced	O
on	O
a	O
90nm	O
process	O
,	O
and	O
included	O
several	O
major	O
design	O
changes	O
,	O
including	O
the	O
addition	O
of	O
an	O
even	O
larger	O
cache	O
(	O
from	O
512	O
KB	O
in	O
the	O
Northwood	O
to	O
1	O
MB	O
,	O
and	O
2	O
MB	O
in	O
Prescott	O
2M	O
)	O
,	O
a	O
much	O
deeper	O
instruction	B-General_Concept
pipeline	I-General_Concept
(	O
31	O
stages	O
as	O
compared	O
to	O
20	O
in	O
the	O
Northwood	O
)	O
,	O
a	O
heavily	O
improved	O
branch	B-General_Concept
predictor	I-General_Concept
,	O
the	O
introduction	O
of	O
the	O
SSE3	B-General_Concept
instructions	O
,	O
and	O
later	O
,	O
the	O
implementation	O
of	O
Intel	O
64	O
,	O
Intel	O
's	O
branding	O
for	O
their	O
compatible	O
implementation	O
of	O
the	O
x86-64	B-Device
64-bit	O
version	O
of	O
the	O
x86	B-Operating_System
microarchitecture	O
(	O
as	O
with	O
hyper-threading	B-Operating_System
,	O
all	O
Prescott	O
chips	O
branded	O
Pentium	B-General_Concept
4	I-General_Concept
HT	O
have	O
hardware	O
to	O
support	O
this	O
feature	O
,	O
but	O
it	O
was	O
initially	O
only	O
enabled	O
on	O
the	O
high-end	O
Xeon	B-Device
processors	O
,	O
before	O
being	O
officially	O
introduced	O
in	O
processors	O
with	O
the	O
Pentium	B-General_Concept
trademark	O
)	O
.	O
</s>
<s>
Power	O
consumption	O
and	O
heat	O
dissipation	O
also	O
became	O
major	O
issues	O
with	O
Prescott	O
,	O
which	O
quickly	O
became	O
the	O
hottest-running	O
,	O
and	O
most	O
power-hungry	O
,	O
of	O
Intel	O
's	O
single-core	O
x86	B-Operating_System
and	O
x86-64	B-Device
processors	O
.	O
</s>
<s>
Intel	O
also	O
released	O
a	O
dual-core	O
processor	O
based	O
on	O
the	O
NetBurst	B-Device
microarchitecture	O
branded	O
Pentium	B-Device
D	I-Device
.	O
The	O
first	O
Pentium	B-Device
D	I-Device
core	O
was	O
codenamed	O
Smithfield	B-Device
,	O
which	O
is	O
actually	O
two	O
Prescott	O
cores	O
in	O
a	O
single	O
die	O
,	O
and	O
later	O
Presler	B-Device
,	O
which	O
consists	O
of	O
two	O
Cedar	O
Mill	O
cores	O
on	O
two	O
separate	O
dies	O
(	O
Cedar	O
Mill	O
being	O
the	O
65nm	B-Algorithm
die-shrink	O
of	O
Prescott	O
)	O
.	O
</s>
<s>
Intel	O
had	O
Netburst-based	O
successors	O
in	O
development	O
called	O
Tejas	B-Device
and	I-Device
Jayhawk	I-Device
with	O
between	O
40	O
and	O
50	O
pipeline	O
stages	O
,	O
but	O
ultimately	O
decided	O
to	O
replace	O
NetBurst	B-Device
with	O
the	O
Core	B-Device
microarchitecture	I-Device
,	O
released	O
in	O
July	O
2006	O
;	O
these	O
successors	O
were	O
more	O
directly	O
derived	O
from	O
the	O
Pentium	B-Device
Pro	I-Device
(	O
P6	B-Device
microarchitecture	I-Device
)	O
.	O
</s>
<s>
The	O
reason	O
for	O
NetBurst	B-Device
's	O
abandonment	O
was	O
the	O
severe	O
heat	O
problems	O
caused	O
by	O
high	O
clock	O
speeds	O
.	O
</s>
<s>
While	O
some	O
Core	O
-	O
and	O
Nehalem-based	O
processors	O
have	O
higher	O
TDPs	O
,	O
most	O
processors	O
are	O
multi-core	O
,	O
so	O
each	O
core	O
gives	O
off	O
a	O
fraction	O
of	O
the	O
maximum	O
TDP	B-General_Concept
,	O
and	O
the	O
highest-clocked	O
Core-based	O
single-core	O
processors	O
give	O
off	O
a	O
maximum	O
of	O
27	O
W	O
of	O
heat	O
.	O
</s>
<s>
The	O
fastest-clocked	O
desktop	O
Pentium	B-General_Concept
4	I-General_Concept
processors	O
(	O
single-core	O
)	O
had	O
TDPs	O
of	O
115	O
W	O
,	O
compared	O
to	O
88	O
W	O
for	O
the	O
fastest	O
clocked	O
mobile	O
versions	O
.	O
</s>
<s>
The	O
Nehalem	B-Device
microarchitecture	I-Device
,	O
the	O
successor	O
to	O
the	O
Core	B-Device
microarchitecture	I-Device
,	O
was	O
supposed	O
to	O
be	O
an	O
evolution	O
of	O
NetBurst	B-Device
according	O
to	O
Intel	O
roadmaps	O
dating	O
back	O
to	O
2000	O
.	O
</s>
<s>
Nehalem	B-Device
reimplements	O
certain	O
features	O
of	O
NetBurst	B-Device
,	O
including	O
the	O
Hyper-Threading	B-Operating_System
technology	I-Operating_System
first	O
introduced	O
in	O
the	O
3.06GHz	O
Northwood	O
core	O
,	O
and	O
L3	O
cache	O
,	O
first	O
implemented	O
on	O
a	O
consumer	O
processor	O
in	O
the	O
Gallatin	O
core	O
used	O
in	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
Extreme	I-General_Concept
Edition	I-General_Concept
.	O
</s>
