<s>
Nehalem	B-Device
is	O
the	O
codename	B-Architecture
for	O
Intel	O
's	O
45	B-Algorithm
nm	I-Algorithm
microarchitecture	B-General_Concept
released	O
in	O
November	O
2008	O
.	O
</s>
<s>
It	O
was	O
used	O
in	O
the	O
first-generation	O
of	O
the	O
Intel	B-Device
Core	I-Device
i5	I-Device
and	O
i7	B-Device
processors	O
,	O
and	O
succeeds	O
the	O
older	O
Core	B-Device
microarchitecture	I-Device
used	O
on	O
Core	B-Device
2	I-Device
processors	I-Device
.	O
</s>
<s>
The	O
term	O
"	O
Nehalem	B-Device
"	O
comes	O
from	O
the	O
Nehalem	B-Device
River	O
.	O
</s>
<s>
Nehalem	B-Device
is	O
built	O
on	O
the	O
45	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
,	O
is	O
able	O
to	O
run	O
at	O
higher	O
clock	O
speeds	O
,	O
and	O
is	O
more	O
energy-efficient	O
than	O
Penryn	B-Device
microprocessors	O
.	O
</s>
<s>
Hyper-threading	B-Operating_System
is	O
reintroduced	O
,	O
along	O
with	O
a	O
reduction	O
in	O
L2	O
cache	O
size	O
,	O
as	O
well	O
as	O
an	O
enlarged	O
L3	O
cache	O
that	O
is	O
shared	O
among	O
all	O
cores	B-Architecture
.	O
</s>
<s>
Nehalem	B-Device
is	O
an	O
architecture	O
that	O
differs	O
radically	O
from	O
NetBurst	B-Device
,	O
while	O
retaining	O
some	O
of	O
the	O
latter	O
's	O
minor	O
features	O
.	O
</s>
<s>
Nehalem	B-Device
later	O
received	O
a	O
die-shrink	O
to	O
32	B-Algorithm
nm	I-Algorithm
with	O
Westmere	B-Device
,	O
and	O
was	O
fully	O
succeeded	O
by	O
"	O
second-generation	O
"	O
Sandy	B-Device
Bridge	I-Device
in	O
January	O
2011	O
.	O
</s>
<s>
Cache	O
line	O
block	O
on	O
L2/L3	O
cache	O
was	O
reduced	O
from	O
128	O
bytes	O
in	O
NetBurst	B-Device
&	O
Conroe/Penryn	O
to	O
64	O
bytes	O
per	O
line	O
in	O
this	O
generation	O
(	O
same	O
size	O
as	O
Yonah	O
and	O
Pentium	O
M	O
)	O
.	O
</s>
<s>
Hyper-threading	B-Operating_System
reintroduced	O
.	O
</s>
<s>
Intel	B-Device
Turbo	I-Device
Boost	I-Device
1.0	O
.	O
</s>
<s>
Instruction	O
Fetch	O
Unit	O
(	O
IFU	O
)	O
containing	O
second-level	O
branch	B-General_Concept
predictor	I-General_Concept
with	O
two	O
level	O
Branch	O
Target	O
Buffer	O
(	O
BTB	O
)	O
and	O
Return	O
Stack	O
Buffer	O
(	O
RSB	O
)	O
.	O
</s>
<s>
Nehalem	B-Device
also	O
supports	O
all	O
predictor	O
types	O
previously	O
used	O
in	O
Intel	O
's	O
processors	O
like	O
Indirect	O
Predictor	O
and	O
Loop	O
Detector	O
.	O
</s>
<s>
sTLB	O
(	O
second	O
level	O
unified	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
)	O
(	O
i.e.	O
</s>
<s>
It	O
has	O
been	O
reported	O
that	O
Nehalem	B-Device
has	O
a	O
focus	O
on	O
performance	O
,	O
thus	O
the	O
increased	O
core	O
size	O
.	O
</s>
<s>
Compared	O
to	O
Penryn	B-Device
,	O
Nehalem	B-Device
has	O
:	O
</s>
<s>
On	O
average	O
,	O
Nehalem	B-Device
provides	O
a	O
1520%	O
clock-for-clock	O
increase	O
in	O
performance	O
per	O
core	O
.	O
</s>
<s>
Overclocking	O
is	O
possible	O
with	O
Bloomfield	B-Device
processors	O
and	O
the	O
X58	B-Device
chipset	O
.	O
</s>
<s>
Lynnfield	B-Device
processors	O
use	O
a	O
PCH	B-Device
removing	O
the	O
need	O
for	O
a	O
northbridge	B-Device
.	O
</s>
<s>
Nehalem	B-Device
processors	O
incorporate	O
SSE	O
4.2	O
SIMD	B-Device
instructions	O
,	O
adding	O
seven	O
new	O
instructions	O
to	O
the	O
SSE	O
4.1	O
set	O
in	O
the	O
Core	B-Device
2	I-Device
series	O
.	O
</s>
<s>
The	O
Nehalem	B-Device
architecture	O
reduces	O
atomic	O
operation	O
latency	O
by	O
50%	O
in	O
an	O
attempt	O
to	O
eliminate	O
overhead	O
on	O
atomic	O
operations	O
such	O
as	O
the	O
LOCK	O
CMPXCHG	O
compare-and-swap	B-Operating_System
instruction	O
.	O
</s>
<s>
Processing	O
Cores	B-Architecture
(	O
interface	O
)	O
Process	O
Die	O
Size	O
million	O
transistors	O
CPUID	O
Model	O
Stepping	O
Mobile	O
Desktop	O
,	O
UP	O
Server	O
DP	O
Server	O
MP	O
Server	O
Eight-Core	O
(	O
Quad-Channel	O
)	O
45	O
nm	O
684	O
mm²	O
2.300	O
206E6	O
46	O
D0	O
Beckton	O
(	O
80604	O
)	O
Quad-Core	B-Architecture
(	O
Triple-Channel	O
)	O
45	O
nm	O
263	O
mm²	O
731	O
106A4106A5	O
26	O
C0/C1D0	O
Bloomfield	B-Device
(	O
80601	O
)	O
Gainestown	O
(	O
80602	O
)	O
Quad-Core	B-Architecture
(	O
Dual-Channel	O
,	O
PCIe	O
)	O
45	O
nm296	O
mm²	O
774	O
106E4106E5	O
30	O
B0B1	O
Clarksfield	B-Device
(	O
80607	O
)	O
Lynnfield	B-Device
(	O
80605	O
)	O
Jasper	O
Forest	O
(	O
80612	O
)	O
Dual-Core	B-Architecture
(	O
Dual-Channel	O
,	O
PCIe	O
,	O
Graphics	O
Core	O
)	O
45	O
nm	O
?	O
</s>
<s>
Lynnfield	B-Device
processors	O
feature	O
16	O
PCIe	O
lanes	O
,	O
which	O
can	O
be	O
used	O
in	O
1x16	O
or	O
2x8	O
configuration	O
.	O
</s>
<s>
Gainestown	O
processors	O
have	O
dual	O
QPI	B-Architecture
links	O
and	O
have	O
a	O
separate	O
set	O
of	O
memory	O
registers	O
for	O
each	O
link	O
in	O
effect	O
,	O
a	O
multiplexed	O
six-channel	O
system	O
.	O
</s>
