<s>
National	O
Semiconductor	O
's	O
IPC-16A	O
PACE	O
,	O
short	O
for	O
"	O
Processing	O
and	O
Control	O
Element	O
"	O
,	O
was	O
the	O
first	O
commercial	O
single-chip	O
16-bit	B-Device
microprocessor	B-Architecture
,	O
announced	O
in	O
late	O
1974	O
.	O
</s>
<s>
It	O
was	O
a	O
single-chip	O
implementation	O
of	O
their	O
early	O
1973	O
five-chip	O
IMP-16	B-Device
architecture	O
,	O
which	O
in	O
turn	O
had	O
been	O
inspired	O
by	O
the	O
Data	B-Device
General	I-Device
Nova	I-Device
minicomputer	B-Architecture
.	O
</s>
<s>
To	O
the	O
basic	O
IMP-16	B-Device
,	O
PACE	O
added	O
a	O
new	O
operational	O
mode	O
,	O
"	O
byte	O
mode	O
"	O
,	O
which	O
was	O
useful	O
for	O
working	O
with	O
8-bit	O
data	O
like	O
ASCII	B-Protocol
text	I-Protocol
.	O
</s>
<s>
Implemented	O
in	O
pMOS	B-Algorithm
,	O
as	O
was	O
common	O
for	O
the	O
era	O
,	O
PACE	O
required	O
three	O
supply	O
voltages	O
and	O
an	O
external	O
clock	O
with	O
enough	O
signal	O
to	O
drive	O
the	O
internal	O
logic	O
.	O
</s>
<s>
Most	O
PACE	O
systems	O
also	O
required	O
the	O
BTE	O
chip	O
to	O
convert	O
the	O
higher	O
internal	O
voltage	O
signals	O
to	O
TTL	B-General_Concept
levels	O
used	O
by	O
the	O
rest	O
of	O
the	O
system	O
.	O
</s>
<s>
The	O
PACE	O
was	O
followed	O
by	O
the	O
INS8900	B-Device
,	O
which	O
had	O
the	O
same	O
architecture	O
but	O
was	O
implemented	O
in	O
nMOS	O
.	O
</s>
<s>
By	O
the	O
time	O
it	O
was	O
available	O
,	O
higher-performance	O
16-bit	B-Device
CPUs	O
were	O
appearing	O
,	O
and	O
the	O
company	O
began	O
to	O
deemphasize	O
sales	O
of	O
the	O
line	O
.	O
</s>
<s>
The	O
PACE	O
was	O
packaged	O
in	O
a	O
40-pin	O
dual	B-Algorithm
in-line	I-Algorithm
package	I-Algorithm
(	O
DIP	B-Algorithm
)	O
,	O
originally	O
in	O
ceramic	O
.	O
</s>
<s>
As	O
it	O
was	O
based	O
on	O
pMOS	B-Algorithm
logic	I-Algorithm
,	O
the	O
PACE	O
series	O
required	O
three	O
supply	O
voltages	O
,	O
+5V	O
(	O
VSS	O
,	O
pin	O
20	O
)	O
,	O
+8V	O
(	O
VBB	O
,	O
pin	O
23	O
)	O
and	O
-12V	O
as	O
the	O
ground	O
level	O
(	O
VGG	O
,	O
pin	O
29	O
)	O
.	O
</s>
<s>
As	O
these	O
signals	O
were	O
also	O
used	O
by	O
external	O
devices	O
,	O
the	O
clock	O
signals	O
were	O
at	O
TTL	B-General_Concept
levels	O
,	O
+5V	O
,	O
in	O
contrast	O
to	O
most	O
pins	O
which	O
were	O
at	O
+8V	O
.	O
</s>
<s>
As	O
the	O
external	O
signals	O
were	O
presented	O
at	O
the	O
+8V	O
,	O
interfacing	O
the	O
system	O
with	O
common	O
devices	O
working	O
at	O
TTL	B-General_Concept
levels	O
was	O
not	O
trivial	O
.	O
</s>
<s>
This	O
worked	O
in	O
conjunction	O
with	O
the	O
PACE	O
to	O
produce	O
a	O
complete	O
set	O
of	O
bus	O
signals	O
at	O
TTL	B-General_Concept
voltages	O
that	O
could	O
then	O
be	O
used	O
to	O
easily	O
interface	O
with	O
most	O
contemporary	O
devices	O
like	O
SRAM	B-Architecture
.	O
</s>
<s>
In	O
order	O
to	O
fit	O
16-bit	B-Device
addresses	O
and	O
data	O
onto	O
a	O
40-pin	O
DIP	B-Algorithm
,	O
the	O
same	O
set	O
of	O
16	O
pins	O
was	O
multiplexed	O
between	O
presenting	O
an	O
address	O
and	O
reading	O
and	O
writing	O
data	O
on	O
separate	O
cycles	O
.	O
</s>
<s>
This	O
required	O
the	O
external	O
devices	O
,	O
like	O
the	O
main	O
memory	O
,	O
to	O
latch	B-General_Concept
the	O
address	O
between	O
cycles	O
.	O
</s>
<s>
National	O
Semiconductor	O
's	O
IMP-16	B-Device
had	O
been	O
inspired	O
by	O
the	O
Data	B-Device
General	I-Device
Nova	I-Device
but	O
had	O
a	O
number	O
of	O
minor	O
differences	O
in	O
its	O
ISA	O
.	O
</s>
<s>
Among	O
these	O
was	O
the	O
handling	O
of	O
the	O
four	O
user-accessible	O
16-bit	B-Device
processor	I-Device
registers	O
.	O
</s>
<s>
In	O
the	O
Nova	O
,	O
the	O
first	O
two	O
registers	O
were	O
general-purpose	O
accumulators	B-General_Concept
and	O
used	O
for	O
most	O
basic	O
arithmetic	O
and	O
logic	O
operations	O
,	O
while	O
the	O
second	O
two	O
could	O
be	O
used	O
as	O
operands	O
or	O
used	O
as	O
index	B-General_Concept
registers	I-General_Concept
.	O
</s>
<s>
The	O
IMP-16	B-Device
followed	O
this	O
model	O
,	O
but	O
the	O
PACE	O
changed	O
a	O
number	O
of	O
instructions	O
so	O
that	O
they	O
operated	O
only	O
on	O
the	O
first	O
accumulator	B-General_Concept
,	O
AC0	O
.	O
</s>
<s>
The	O
original	O
Nova	O
did	O
not	O
implement	O
a	O
stack	B-Application
in	O
hardware	O
,	O
although	O
this	O
was	O
added	O
in	O
the	O
later	O
Nova	O
3	O
models	O
starting	O
in	O
1975	O
.	O
</s>
<s>
PACE	O
implemented	O
a	O
different	O
style	O
of	O
stack	B-Application
using	O
a	O
new	O
Stack	B-Application
Pointer	O
(	O
SP	O
)	O
register	O
which	O
was	O
automatically	O
incremented	O
and	O
decremented	O
when	O
and	O
instructions	O
were	O
encountered	O
.	O
</s>
<s>
The	O
Program	O
Counter	O
(	O
PC	O
)	O
was	O
automatically	O
pushed	O
or	O
pulled	O
to	O
the	O
stack	B-Application
during	O
subroutine	O
calls	O
and	O
returns	O
.	O
</s>
<s>
The	O
CPU	O
had	O
ten	O
16-bit	B-Device
memory	O
locations	O
that	O
held	O
the	O
topmost	O
stack	B-Application
values	O
.	O
</s>
<s>
A	O
unique	O
feature	O
of	O
the	O
PACE	O
is	O
that	O
when	O
the	O
stack	B-Application
fills	O
and	O
another	O
push	O
is	O
attempted	O
,	O
or	O
when	O
it	O
is	O
empty	O
and	O
a	O
pull	O
is	O
attempted	O
,	O
an	O
interrupt	B-Application
is	O
generated	O
.	O
</s>
<s>
This	O
is	O
normally	O
used	O
to	O
call	O
interrupt	B-General_Concept
handler	I-General_Concept
code	O
that	O
copies	O
some	O
or	O
all	O
of	O
the	O
values	O
out	O
of	O
the	O
stack	B-Application
into	O
main	O
memory	O
,	O
and	O
then	O
empties	O
the	O
stack	B-Application
.	O
</s>
<s>
This	O
allows	O
the	O
internal	O
stack	B-Application
registers	O
to	O
be	O
used	O
like	O
a	O
cache	B-General_Concept
of	O
a	O
larger	O
memory-based	O
stack	B-Application
.	O
</s>
<s>
The	O
Status	O
and	O
Control	O
Flag	O
register	O
was	O
also	O
16-bits	B-Device
wide	O
.	O
</s>
<s>
LINK	O
is	O
normally	O
handled	O
using	O
the	O
carry	B-Algorithm
flag	I-Algorithm
in	O
most	O
microcomputer	O
CPU	O
designs	O
,	O
but	O
having	O
two	O
separate	O
flags	O
is	O
more	O
common	O
in	O
minicomputers	B-Architecture
where	O
there	O
are	O
enough	O
available	O
status	O
bits	O
,	O
as	O
it	O
allows	O
the	O
two	O
to	O
be	O
tracked	O
separately	O
during	O
a	O
series	O
of	O
shift/rotate	O
and	O
add	O
instructions	O
,	O
which	O
is	O
a	O
common	O
sequence	O
.	O
</s>
<s>
The	O
IN	O
EN	O
flag	O
,	O
normally	O
1	O
,	O
allows	O
interrupts	B-Application
to	O
be	O
enabled	O
or	O
disabled	O
.	O
</s>
<s>
One	O
unique	O
feature	O
of	O
the	O
PACE	O
,	O
not	O
present	O
in	O
the	O
IMP-16	B-Device
,	O
is	O
the	O
BYTE	O
flag	O
.	O
</s>
<s>
This	O
allows	O
for	O
easier	O
processing	O
of	O
8-bit	O
data	O
like	O
ASCII	B-Protocol
text	I-Protocol
.	O
</s>
<s>
Bits	O
1	O
through	O
5	O
are	O
the	O
IE1	O
thorugh	O
IE5	O
flags	O
,	O
which	O
are	O
used	O
to	O
control	O
interrupts	B-Application
in	O
a	O
priority	O
fashion	O
.	O
</s>
<s>
IE1	O
is	O
set	O
only	O
in	O
the	O
case	O
of	O
a	O
stack	B-Application
overflow	O
.	O
</s>
<s>
The	O
other	O
four	O
can	O
be	O
used	O
to	O
disable	O
individual	O
interrupt	B-Application
lines	I-Application
,	O
or	O
more	O
commonly	O
,	O
produce	O
a	O
binary	O
value	O
from	O
0	O
to	O
15	O
that	O
external	O
devices	O
use	O
to	O
determine	O
whether	O
or	O
not	O
they	O
should	O
perform	O
an	O
interrupt	B-Application
.	O
</s>
<s>
For	O
instance	O
,	O
if	O
the	O
value	O
in	O
these	O
flags	O
adds	O
up	O
to	O
5	O
,	O
any	O
device	O
with	O
an	O
interrupt	B-Application
value	O
of	O
5	O
or	O
lower	O
(	O
1	O
is	O
the	O
highest	O
priority	O
)	O
can	O
express	O
it	O
,	O
a	O
device	O
wishing	O
to	O
call	O
a	O
lower	O
priority	O
,	O
say	O
7	O
,	O
is	O
being	O
instructed	O
to	O
hold	O
it	O
.	O
</s>
<s>
In	O
contrast	O
to	O
most	O
microcomputer	O
designs	O
of	O
the	O
era	O
,	O
the	O
PACE	O
did	O
not	O
use	O
variable-length	O
instructions	O
,	O
all	O
instructions	O
used	O
16	B-Device
bits	I-Device
.	O
</s>
<s>
The	O
16-bit	B-Device
words	O
were	O
broken	O
into	O
a	O
series	O
of	O
bit	O
fields	O
for	O
the	O
instruction	O
format	O
.	O
</s>
<s>
The	O
top	O
six	O
bits	O
,	O
10	O
through	O
15	O
,	O
held	O
the	O
opcode	B-Language
,	O
while	O
bits	O
8	O
(	O
R	O
for	O
Relative	O
)	O
and	O
9	O
(	O
X	O
for	O
indeX	O
)	O
indicated	O
the	O
addressing	O
mode	O
.	O
</s>
<s>
This	O
meant	O
that	O
an	O
arbitrary	O
memory	O
location	O
could	O
not	O
be	O
specified	O
directly	O
;	O
several	O
different	O
systems	O
were	O
used	O
to	O
build	O
the	O
required	O
16-bit	B-Device
address	O
from	O
the	O
8-bit	O
value	O
.	O
</s>
<s>
There	O
were	O
43	O
instructions	O
and	O
45	O
opcodes	B-Language
,	O
with	O
two	O
opcodes	B-Language
each	O
for	O
and	O
(	O
see	O
below	O
)	O
.	O
</s>
<s>
Setting	O
the	O
X	O
bit	O
to	O
1	O
turned	O
on	O
indexing	O
,	O
using	O
the	O
eight	O
bits	O
in	O
addition	O
to	O
the	O
values	O
in	O
the	O
index	B-General_Concept
registers	I-General_Concept
,	O
with	O
R	O
at	O
0	O
it	O
would	O
add	O
the	O
value	O
in	O
AC2	O
,	O
and	O
setting	O
it	O
to	O
1	O
used	O
AC3	O
instead	O
.	O
</s>
<s>
Indicating	O
indirect	O
addressing	O
used	O
separate	O
opcodes	B-Language
,	O
as	O
opposed	O
to	O
using	O
the	O
addressing	O
indication	O
bits	O
.	O
</s>
<s>
It	O
would	O
then	O
read	O
the	O
16-bit	B-Device
value	O
in	O
that	O
memory	O
location	O
and	O
then	O
load	O
or	O
store	O
from	O
that	O
address	O
.	O
</s>
<s>
When	O
combined	O
with	O
the	O
X	O
flag	O
,	O
the	O
8-bit	O
offset	O
is	O
first	O
added	O
or	O
subtracted	O
from	O
the	O
indicated	O
index	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
This	O
style	O
of	O
looping	O
control	O
is	O
common	O
in	O
minicomputers	B-Architecture
,	O
but	O
not	O
so	O
in	O
microcomputer	O
designs	O
.	O
</s>
<s>
Continued	O
improvement	O
in	O
semiconductor	B-Architecture
fabrication	I-Architecture
in	O
the	O
early	O
1970s	O
led	O
to	O
the	O
introduction	O
of	O
the	O
NMOS	B-Algorithm
logic	I-Algorithm
concept	O
,	O
or	O
nMOS	O
.	O
</s>
<s>
This	O
type	O
of	O
logic	O
has	O
the	O
significant	O
advantage	O
that	O
its	O
internal	O
transistors	B-Application
do	O
not	O
require	O
a	O
large	O
voltage	O
on	O
the	O
substrate	O
layer	O
,	O
like	O
pMOS	B-Algorithm
.	O
</s>
<s>
In	O
practical	O
terms	O
,	O
this	O
means	O
an	O
nMOS	O
processor	O
can	O
operate	O
with	O
only	O
two	O
input	O
voltages	O
rather	O
than	O
three	O
,	O
and	O
the	O
positive	O
supply	O
can	O
be	O
set	O
to	O
+5V	O
,	O
making	O
interfacing	O
with	O
TTL	B-General_Concept
circuits	O
trivially	O
easy	O
.	O
</s>
<s>
National	O
Semiconductor	O
took	O
advantage	O
of	O
this	O
technique	O
with	O
a	O
redesign	O
of	O
the	O
PACE	O
in	O
nMOS	O
to	O
create	O
the	O
INS8900	B-Device
.	O
</s>
<s>
The	O
most	O
important	O
change	O
in	O
terms	O
of	O
usage	O
was	O
that	O
the	O
various	O
signal	O
pins	O
now	O
worked	O
at	O
TTL	B-General_Concept
voltages	O
,	O
allowing	O
them	O
to	O
communicate	O
directly	O
with	O
external	O
systems	O
like	O
memory	O
.	O
</s>
<s>
This	O
change	O
did	O
not	O
address	O
the	O
issue	O
of	O
having	O
to	O
latch	B-General_Concept
the	O
address	O
on	O
the	O
shared	O
data/address	O
bus	O
,	O
but	O
it	O
did	O
make	O
such	O
latching	O
much	O
easier	O
.	O
</s>
<s>
Instead	O
of	O
requiring	O
the	O
relatively	O
complex	O
BTE	O
chip	O
,	O
this	O
task	O
could	O
now	O
be	O
performed	O
by	O
common	O
TTL	B-General_Concept
components	O
,	O
although	O
National	O
Semiconductor	O
suggested	O
their	O
own	O
INS8208	O
and	O
INS8212	O
for	O
this	O
purpose	O
.	O
</s>
<s>
Notable	O
among	O
these	O
was	O
a	O
problem	O
with	O
the	O
interrupt	B-Application
that	O
was	O
triggered	O
when	O
the	O
stack	B-Application
filled	O
.	O
</s>
<s>
In	O
the	O
PACE	O
this	O
did	O
not	O
work	O
properly	O
;	O
if	O
the	O
interrupt	B-Application
arrived	O
at	O
exactly	O
the	O
same	O
time	O
as	O
a	O
NIR3	O
or	O
NIR5	O
,	O
the	O
wrong	O
interrupt	B-Application
code	O
would	O
be	O
called	O
from	O
location	O
0	O
rather	O
than	O
2	O
.	O
</s>
<s>
There	O
were	O
similar	O
problems	O
when	O
a	O
level-0	O
interrupt	B-Application
occurred	O
within	O
a	O
12	O
cycles	O
of	O
other	O
interrupts	B-Application
,	O
causing	O
the	O
wrong	O
code	O
to	O
be	O
called	O
.	O
</s>
<s>
Although	O
the	O
PACE	O
ran	O
at	O
a	O
relatively	O
fast	O
clock	O
speed	O
for	O
the	O
era	O
,	O
the	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
was	O
implemented	O
using	O
microcode	B-Device
and	O
the	O
multiplexed	O
bus	O
required	O
two	O
cycles	O
for	O
each	O
memory	O
access	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
a	O
typical	O
instruction	O
took	O
about	O
12	O
to	O
30	O
microseconds	O
to	O
complete	O
,	O
making	O
it	O
about	O
the	O
same	O
speed	O
as	O
contemporary	O
8-bit	O
processors	O
like	O
the	O
Intel	B-General_Concept
8080	I-General_Concept
.	O
</s>
<s>
This	O
still	O
provided	O
an	O
advantage	O
when	O
working	O
with	O
larger	O
data	O
,	O
for	O
instance	O
in	O
a	O
floating	B-Algorithm
point	I-Algorithm
library	O
,	O
as	O
that	O
single	O
instruction	O
could	O
process	O
twice	O
as	O
much	O
data	O
in	O
a	O
single	O
operation	O
.	O
</s>
