<s>
A	O
nanoelectromechanical	O
(	O
NEM	O
)	O
relay	O
is	O
an	O
electrically	O
actuated	O
switch	O
that	O
is	O
built	O
on	O
the	O
nanometer	O
scale	O
using	O
semiconductor	B-Architecture
fabrication	I-Architecture
techniques	O
.	O
</s>
<s>
While	O
the	O
mechanical	O
nature	O
of	O
NEM	O
relays	O
makes	O
them	O
switch	O
much	O
slower	O
than	O
solid-state	B-Algorithm
relays	I-Algorithm
,	O
they	O
have	O
many	O
advantageous	O
properties	O
,	O
such	O
as	O
zero	O
current	O
leakage	O
and	O
low	O
power	O
consumption	O
,	O
which	O
make	O
them	O
potentially	O
useful	O
in	O
next	O
generation	O
computing	O
.	O
</s>
<s>
Coating	O
contact	O
surfaces	O
with	O
platinum	B-Operating_System
can	O
reduce	O
achievable	O
contact	O
resistance	O
to	O
as	O
low	O
as	O
3	O
kΩ	O
.	O
</s>
<s>
This	O
property	O
is	O
very	O
useful	O
in	O
applications	O
where	O
information	O
needs	O
to	O
be	O
stored	O
in	O
the	O
circuit	O
,	O
such	O
as	O
in	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
.	O
</s>
<s>
NEM	O
relays	O
are	O
usually	O
fabricated	O
using	O
surface	O
micromachining	O
techniques	O
typical	O
of	O
microelectromechanical	B-Architecture
systems	I-Architecture
(	O
MEMS	B-Architecture
)	O
.	O
</s>
<s>
Laterally	O
actuated	O
relays	O
are	O
constructed	O
by	O
first	O
depositing	O
two	O
or	O
more	O
layers	O
of	O
material	O
on	O
a	O
silicon	B-Architecture
wafer	I-Architecture
.	O
</s>
<s>
The	O
layer	O
below	O
is	O
then	O
selectively	O
etched	O
away	O
,	O
leaving	O
thin	O
structures	O
,	O
such	O
as	O
the	O
relay	O
's	O
beam	O
,	O
cantilevered	O
above	O
the	O
wafer	B-Architecture
,	O
and	O
free	O
to	O
bend	O
laterally	O
.	O
</s>
<s>
NEM	O
relays	O
can	O
be	O
fabricated	O
using	O
a	O
back	B-Algorithm
end	I-Algorithm
of	I-Algorithm
line	I-Algorithm
compatible	O
process	O
,	O
allowing	O
them	O
to	O
be	O
built	O
on	O
top	O
of	O
CMOS	B-Device
.	O
</s>
<s>
For	O
example	O
,	O
a	O
CMOS-NEM	O
relay	O
hybrid	O
inverter	O
occupies	O
0.03µm2	O
,	O
one-third	O
the	O
area	O
of	O
a	O
45nm	O
CMOS	B-Device
inverter	O
.	O
</s>
<s>
In	O
the	O
1980s	O
,	O
surface	O
micromachining	O
techniques	O
were	O
developed	O
and	O
the	O
technology	O
was	O
applied	O
to	O
the	O
fabrication	B-Architecture
of	O
switches	O
,	O
allowing	O
for	O
smaller	O
,	O
more	O
efficient	O
relays	O
.	O
</s>
<s>
A	O
major	O
early	O
application	O
of	O
MEMS	B-Architecture
relays	O
was	O
for	O
switching	O
radio	O
frequency	O
signals	O
at	O
which	O
solid-state	B-Algorithm
relays	I-Algorithm
had	O
poor	O
performance	O
.	O
</s>
<s>
By	O
shrinking	O
dimensions	O
below	O
one	O
micrometer	O
,	O
and	O
moving	O
into	O
the	O
nano	O
scale	O
,	O
MEMS	B-Architecture
switches	O
have	O
achieved	O
switching	O
times	O
in	O
the	O
ranges	O
of	O
hundreds	O
of	O
nanoseconds	O
.	O
</s>
<s>
Due	O
to	O
transistor	O
leakage	O
,	O
there	O
is	O
a	O
limit	O
to	O
the	O
theoretical	O
efficiency	O
of	O
CMOS	B-Device
logic	O
.	O
</s>
<s>
While	O
NEM	O
relays	O
have	O
significant	O
switching	O
delays	O
,	O
their	O
small	O
size	O
and	O
fast	O
switching	O
speed	O
when	O
compared	O
to	O
other	O
relays	O
means	O
that	O
mechanical	B-Device
computing	I-Device
utilizing	O
NEM	O
Relays	O
could	O
prove	O
a	O
viable	O
replacement	O
for	O
typical	O
CMOS	B-Device
based	O
integrated	O
circuits	O
,	O
and	O
break	O
this	O
CMOS	B-Device
efficiency	O
barrier	O
.	O
</s>
<s>
On	O
the	O
other	O
hand	O
,	O
transistor	O
logic	O
has	O
to	O
be	O
implemented	O
in	O
small	O
cycles	B-General_Concept
of	O
calculations	O
,	O
because	O
their	O
high	O
resistance	O
does	O
not	O
allow	O
many	O
transistors	O
to	O
be	O
chained	O
together	O
while	O
maintaining	O
signal	O
integrity	O
.	O
</s>
<s>
Therefore	O
,	O
it	O
would	O
be	O
possible	O
to	O
create	O
a	O
mechanical	B-Device
computer	I-Device
using	O
NEM	O
relays	O
that	O
operates	O
at	O
a	O
much	O
lower	O
clock	O
speed	O
than	O
CMOS	B-Device
logic	O
,	O
but	O
performs	O
larger	O
,	O
more	O
complex	O
calculations	O
during	O
each	O
cycle	O
.	O
</s>
<s>
This	O
would	O
allow	O
a	O
NEM	O
relay	O
based	O
logic	O
to	O
perform	O
to	O
standards	O
comparable	O
to	O
current	O
CMOS	B-Device
logic	O
.	O
</s>
<s>
NEM	O
relays	O
do	O
not	O
rely	O
on	O
the	O
electrical	O
properties	O
of	O
materials	O
to	O
actuate	O
,	O
so	O
a	O
mechanical	B-Device
computer	I-Device
utilizing	O
NEM	O
relays	O
would	O
be	O
able	O
to	O
operate	O
in	O
such	O
conditions	O
.	O
</s>
<s>
The	O
zero	O
leakage	O
current	O
,	O
low	O
energy	O
usage	O
,	O
and	O
ability	O
to	O
be	O
layered	O
on	O
top	O
of	O
CMOS	B-Device
properties	O
of	O
NEM	O
relays	O
make	O
them	O
a	O
promising	O
candidate	O
for	O
usage	O
as	O
routing	O
switches	O
in	O
Field-programmable	B-Architecture
gate	I-Architecture
arrays	I-Architecture
(	O
FPGA	B-Architecture
)	O
.	O
</s>
<s>
A	O
FPGA	B-Architecture
utilizing	O
a	O
NEM	O
relay	O
to	O
replace	O
each	O
routing	O
switch	O
and	O
its	O
corresponding	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
block	O
could	O
allow	O
for	O
a	O
significant	O
reduction	O
in	O
programming	O
delay	O
,	O
power	O
leakage	O
,	O
and	O
chip	O
area	O
compared	O
to	O
a	O
typical	O
22nm	B-Algorithm
CMOS	B-Device
based	O
FPGA	B-Architecture
.	O
</s>
<s>
This	O
area	O
reduction	O
mainly	O
comes	O
from	O
the	O
fact	O
that	O
the	O
NEM	O
relay	O
routing	O
layer	O
can	O
be	O
built	O
on	O
top	O
of	O
the	O
CMOS	B-Device
layer	O
of	O
the	O
FPGA	B-Architecture
.	O
</s>
