<s>
The	O
NVIDIA	O
Deep	B-General_Concept
Learning	I-General_Concept
Accelerator	I-General_Concept
(	O
NVDLA	B-Algorithm
)	O
is	O
an	O
open-source	O
hardware	O
neural	B-Architecture
network	I-Architecture
AI	B-General_Concept
accelerator	I-General_Concept
created	O
by	O
Nvidia	O
.	O
</s>
<s>
The	O
accelerator	O
is	O
written	O
in	O
Verilog	B-Language
and	O
is	O
configurable	O
and	O
scalable	O
to	O
meet	O
many	O
different	O
architecture	O
needs	O
.	O
</s>
<s>
NVDLA	B-Algorithm
is	O
merely	O
an	O
accelerator	O
and	O
any	O
process	O
must	O
be	O
scheduled	O
and	O
arbitered	O
by	O
an	O
outside	O
entity	O
such	O
as	O
a	O
CPU	O
.	O
</s>
<s>
NVDLA	B-Algorithm
is	O
available	O
for	O
product	O
development	O
as	O
part	O
of	O
Nvidia	O
's	O
Jetson	O
Xavier	O
NX	O
,	O
a	O
small	O
circuit	O
board	O
in	O
a	O
form	O
factor	O
about	O
the	O
size	O
of	O
a	O
credit	O
card	O
which	O
includes	O
a	O
6-core	O
ARMv8.2	O
64-bit	O
CPU	O
,	O
an	O
integrated	O
384-core	O
Volta	B-General_Concept
GPU	O
with	O
48	O
Tensor	O
Cores	O
,	O
and	O
dual	O
NVDLA	B-Algorithm
"	O
engines	O
"	O
,	O
as	O
described	O
in	O
their	O
own	O
press	O
release	O
.	O
</s>
<s>
Nvidia	O
claims	O
the	O
product	O
will	O
deliver	O
14	O
TOPS	O
(	O
tera	O
operations	O
per	O
second	O
)	O
of	O
compute	O
under	O
10	O
W	O
.	O
Applications	O
broadly	O
include	O
edge	B-Device
computing	I-Device
inference	O
engines	O
,	O
including	O
object	O
recognition	O
for	O
autonomous	O
driving	O
.	O
</s>
<s>
Nvidia	O
's	O
involvement	O
with	O
open	O
hardware	O
includes	O
the	O
use	O
of	O
RISC-V	B-Device
processors	O
as	O
part	O
of	O
their	O
GPU	O
product	O
line-up	O
.	O
</s>
