<s>
The	O
NVAX	B-Device
is	O
a	O
CMOS	B-Device
microprocessor	B-Architecture
developed	O
and	O
produced	O
by	O
Digital	O
Equipment	O
Corporation	O
(	O
DEC	O
)	O
that	O
implemented	O
the	O
VAX	B-Device
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
.	O
</s>
<s>
A	O
variant	O
of	O
the	O
NVAX	B-Device
,	O
the	O
NVAX+	B-Device
,	O
differed	O
in	O
the	O
bus	O
interface	O
and	O
external	O
cache	O
supported	O
,	O
but	O
was	O
otherwise	O
identical	O
in	O
regards	O
to	O
microarchitecture	O
.	O
</s>
<s>
The	O
NVAX+	B-Device
was	O
designed	O
to	O
have	O
the	O
same	O
bus	O
as	O
the	O
DECchip	B-General_Concept
21064	I-General_Concept
,	O
allowing	O
drop-in	O
replacement	O
.	O
</s>
<s>
The	O
NVAX	B-Device
and	O
NVAX+	B-Device
was	O
used	O
in	O
late-model	O
VAX	B-Device
systems	O
released	O
in	O
1991	O
such	O
as	O
the	O
MicroVAX	B-Device
3100	I-Device
,	O
VAXstation	B-Device
4000	I-Device
,	O
VAX	B-Device
4000	I-Device
,	O
VAX	B-Device
6000	I-Device
,	O
VAX	B-Device
7000/10000	I-Device
and	O
VAXft	B-Device
.	O
</s>
<s>
Although	O
Digital	O
updated	O
the	O
design	O
throughout	O
the	O
early	O
1990s	O
,	O
the	O
processors	O
,	O
and	O
the	O
VAX	B-Device
platform	O
itself	O
,	O
were	O
ultimately	O
superseded	O
by	O
the	O
introduction	O
of	O
the	O
DECchip	B-General_Concept
21064	I-General_Concept
,	O
an	O
implementation	O
of	O
the	O
Alpha	B-Device
(	O
then	O
Alpha	B-Device
AXP	I-Device
)	O
architecture	O
,	O
and	O
the	O
resulting	O
systems	O
in	O
November	O
1992	O
.	O
</s>
<s>
The	O
NVAX	B-Device
was	O
offered	O
at	O
a	O
variety	O
of	O
clock	O
speeds	O
,	O
83.3	O
MHz	O
(	O
12	O
ns	O
)	O
,	O
71	O
MHz	O
(	O
14	O
ns	O
)	O
and	O
62.5	O
MHz	O
(	O
16	O
ns	O
)	O
,	O
while	O
the	O
NVAX+	B-Device
is	O
clocked	O
at	O
a	O
frequency	O
of	O
90.9	O
MHz	O
(	O
11	O
ns	O
)	O
.	O
</s>
<s>
The	O
NVAX	B-Device
offered	O
about	O
25	O
VAX	B-Device
Unit	O
of	O
Performance	O
(	O
VUPs	O
)	O
,	O
while	O
the	O
NVAX+	B-Device
was	O
roughly	O
35	O
VUPs	O
.	O
</s>
<s>
This	O
was	O
only	O
slightly	O
less	O
than	O
the	O
VAX	B-Device
9000	I-Device
mainframe	O
's	O
roughly	O
40	O
VUPs	O
,	O
but	O
available	O
in	O
a	O
desktop	O
form	O
factor	O
.	O
</s>
<s>
The	O
final	O
model	O
in	O
the	O
series	O
was	O
the	O
NVAX++	B-Device
,	O
or	O
NV5	O
,	O
offering	O
50	O
VUPs	O
.	O
</s>
<s>
This	O
was	O
the	O
last	O
VAX	B-Device
processor	O
,	O
DEC	O
had	O
moved	O
entirely	O
to	O
the	O
DEC	B-Device
Alpha	I-Device
after	O
that	O
point	O
.	O
</s>
<s>
NVAX	B-Device
contained	O
1.3	O
million	O
transistors	O
on	O
a	O
die	O
measuring	O
16.2	O
by	O
14.6	O
mm	O
in	O
size	O
(	O
236.52	O
mm²	O
)	O
.	O
</s>
<s>
The	O
die	O
was	O
fabricated	B-Architecture
in	O
Digital	O
's	O
fourth-generation	O
CMOS	B-Device
process	O
,	O
CMOS-4	O
,	O
a	O
0.75	O
µm	O
process	O
with	O
three	O
layers	O
of	O
aluminium	O
interconnect	O
.	O
</s>
<s>
The	O
NVAX	B-Device
is	O
packaged	O
in	O
a	O
339-pin	O
pin	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
.	O
</s>
<s>
The	O
NVAX	B-Device
was	O
offered	O
at	O
a	O
variety	O
of	O
clock	O
speeds	O
,	O
83.3	O
MHz	O
(	O
12	O
ns	O
)	O
,	O
71	O
MHz	O
(	O
14	O
ns	O
)	O
and	O
62.5	O
MHz	O
(	O
16	O
ns	O
)	O
,	O
while	O
the	O
NVAX+	B-Device
is	O
clocked	O
at	O
a	O
frequency	O
of	O
90.9	O
MHz	O
(	O
11	O
ns	O
)	O
.	O
</s>
<s>
The	O
NVAX	B-Device
offered	O
about	O
25	O
VAX	B-Device
Unit	O
of	O
Performance	O
(	O
VUPs	O
)	O
.	O
</s>
<s>
The	O
NVAX+	B-Device
,	O
introduced	O
at	O
the	O
same	O
time	O
,	O
was	O
identical	O
in	O
terms	O
of	O
the	O
processor	O
design	O
but	O
used	O
a	O
different	O
bus	O
,	O
cache	O
system	O
and	O
its	O
external	O
connection	O
was	O
a	O
431-pin	O
array	O
.	O
</s>
<s>
These	O
were	O
identical	O
to	O
those	O
on	O
the	O
Alpha	B-Device
,	O
allowing	O
an	O
NVAX+	B-Device
machine	O
to	O
be	O
upgraded	O
to	O
an	O
Alpha	B-Device
simply	O
by	O
changing	O
the	O
CPU	O
.	O
</s>
<s>
These	O
changes	O
also	O
allowed	O
it	O
to	O
operate	O
with	O
slightly	O
higher	O
performance	O
,	O
and	O
the	O
NVAX+	B-Device
ran	O
at	O
roughly	O
35	O
VUPs	O
.	O
</s>
<s>
This	O
was	O
only	O
slightly	O
less	O
than	O
the	O
VAX	B-Device
9000	I-Device
mainframe	O
's	O
roughly	O
40	O
VUPs	O
.	O
</s>
<s>
In	O
1994	O
,	O
the	O
NVAX++	B-Device
(	O
also	O
known	O
as	O
NV5	O
)	O
was	O
introduced	O
in	O
VAX	B-Device
7000	I-Device
Model	O
7x0	O
and	O
VAX	B-Device
10000	I-Device
Model	O
7x0	O
systems	O
.	O
</s>
<s>
It	O
operated	O
at	O
133	O
MHz	O
(	O
7.5	O
ns	O
)	O
and	O
was	O
fabricated	B-Architecture
in	O
Digital	O
's	O
fifth-generation	O
CMOS	B-Device
process	O
,	O
CMOS-5	O
,	O
a	O
0.50	O
µm	O
process	O
.	O
</s>
<s>
In	O
1996	O
,	O
a	O
170.9	O
MHz	O
NV5	O
was	O
introduced	O
,	O
used	O
in	O
the	O
VAX	B-Device
7000/10000	I-Device
Model	O
8x0	O
.	O
</s>
<s>
The	O
NVAX	B-Device
is	O
partitioned	O
into	O
five	O
semi-autonomous	O
units	O
,	O
the	O
I-box	O
,	O
E-box	O
,	O
F-box	O
,	O
M-box	O
and	O
C-box	O
.	O
</s>
<s>
The	O
NVAX	B-Device
is	O
macropipelined	O
.	O
</s>
<s>
Multiple	O
VAX	B-Device
macroinstructions	O
are	O
processed	O
in	O
parallel	O
by	O
autonomous	O
units	O
,	O
which	O
have	O
their	O
own	O
micropipelines	O
.	O
</s>
<s>
The	O
I-box	O
fetches	O
and	O
decodes	O
VAX	B-Device
instructions	O
.	O
</s>
<s>
It	O
is	O
controlled	O
by	O
microcode	B-Device
from	O
a	O
1,600	O
-word	O
control	B-General_Concept
store	I-General_Concept
with	O
the	O
capability	O
to	O
patch	O
20	O
words	O
.	O
</s>
