<s>
While	O
flash	B-Device
memory	I-Device
remains	O
one	O
of	O
the	O
most	O
popular	O
storages	O
in	O
embedded	B-Architecture
systems	I-Architecture
because	O
of	O
its	O
non-volatility	B-General_Concept
,	O
shock-resistance	O
,	O
small	O
size	O
,	O
and	O
low	O
energy	O
consumption	O
,	O
its	O
application	O
has	O
grown	O
much	O
beyond	O
its	O
original	O
design	O
.	O
</s>
<s>
Based	O
on	O
its	O
original	O
design	O
,	O
NOR	O
flash	B-Device
memory	I-Device
is	O
designed	O
to	O
store	O
binary	O
code	O
of	O
programs	O
because	O
it	O
supports	O
XIP	B-Application
(	O
eXecute-In-Place	B-Application
)	O
and	O
high	O
performance	O
in	O
read	O
operations	O
,	O
while	O
NAND	O
flash	B-Device
memory	I-Device
is	O
used	O
as	O
a	O
data	O
storage	O
because	O
of	O
its	O
lower	O
price	O
and	O
higher	O
performance	O
in	O
write/erase	O
operations	O
,	O
compared	O
to	O
NOR	O
flash	O
.	O
</s>
<s>
The	O
replacement	O
depends	O
on	O
well-designed	O
management	O
of	O
flash	B-Device
memory	I-Device
,	O
which	O
is	O
carried	O
out	O
by	O
either	O
software	O
on	O
a	O
host	O
system	O
(	O
as	O
a	O
raw	O
medium	O
)	O
or	O
hardware	O
circuits/firmware	O
inside	O
its	O
devices	O
.	O
</s>
<s>
The	O
prediction	O
mechanism	O
collects	O
the	O
access	O
patterns	O
of	O
program	O
execution	O
to	O
construct	O
a	O
prediction	O
graph	O
by	O
adopting	O
the	O
working	B-General_Concept
set	I-General_Concept
concept	O
.	O
</s>
<s>
According	O
to	O
the	O
prediction	O
graph	O
,	O
the	O
prediction	O
mechanism	O
prefetches	O
data	O
(	O
/code	O
)	O
to	O
the	O
SRAM	B-Architecture
cache	B-General_Concept
,	O
so	O
as	O
to	O
reduce	O
the	O
cache	B-General_Concept
miss	O
rate	O
.	O
</s>
<s>
Different	O
from	O
the	O
popular	O
caching	B-General_Concept
ideas	O
in	O
the	O
memory	B-General_Concept
hierarchy	I-General_Concept
,	O
this	O
approach	O
aims	O
at	O
an	O
application-oriented	O
caching	B-General_Concept
mechanism	O
,	O
which	O
adopts	O
prediction-assisted	O
prefetching	O
based	O
on	O
given	O
execution	O
traces	O
of	O
applications	O
.	O
</s>
<s>
The	O
designs	O
of	O
embedded	B-Architecture
systems	I-Architecture
are	O
considered	O
with	O
a	O
limited	O
set	O
of	O
applications	O
,	O
such	O
as	O
a	O
set	O
of	O
selected	O
system	O
programs	O
in	O
mobile	O
phones	O
or	O
arcade	O
games	O
of	O
amusement-park	O
machines	O
.	O
</s>
<s>
Besides	O
,	O
SRAM	B-Architecture
capacity	O
and	O
computing	O
power	O
are	O
constrained	O
in	O
the	O
implementation	O
.	O
</s>
<s>
Four	O
essential	O
components	O
are	O
included	O
in	O
the	O
hardware	O
design	O
:	O
host	O
interface	O
,	O
SRAM	B-Architecture
(	O
cache	B-General_Concept
)	O
,	O
NAND	O
flash	B-Device
memory	I-Device
,	O
and	O
control	O
logic	O
.	O
</s>
<s>
In	O
order	O
to	O
fill	O
up	O
the	O
performance	O
gap	O
between	O
NAND	O
and	O
NOR	O
,	O
SRAM	B-Architecture
serves	O
as	O
a	O
cache	B-General_Concept
layer	O
for	O
data	O
access	O
over	O
NAND	O
.	O
</s>
<s>
The	O
host	O
interface	O
is	O
responsible	O
to	O
the	O
communication	O
with	O
the	O
host	O
system	O
via	O
address	O
and	O
data	B-General_Concept
buses	I-General_Concept
.	O
</s>
<s>
Most	O
importantly	O
,	O
the	O
control	O
logic	O
manages	O
the	O
caching	B-General_Concept
activity	O
and	O
provides	O
the	O
service	O
emulation	O
of	O
NOR	O
flash	O
with	O
NAND	O
flash	O
and	O
SRAM	B-Architecture
;	O
it	O
must	O
have	O
an	O
intelligent	O
prediction	O
mechanism	O
implemented	O
to	O
improve	O
the	O
system	O
performance	O
.	O
</s>
<s>
There	O
are	O
two	O
major	O
components	O
in	O
the	O
control	O
logic	O
:	O
The	O
converter	O
emulates	O
NOR	O
flash	O
access	O
over	O
NAND	O
flash	O
with	O
an	O
SRAM	B-Architecture
cache	B-General_Concept
,	O
where	O
address	O
translation	O
must	O
be	O
done	O
from	O
byte	O
addressing	O
(	O
for	O
NOR	O
)	O
to	O
Logical	B-Device
Block	I-Device
Address	I-Device
(	O
LBA	O
)	O
addressing	O
(	O
for	O
NAND	O
)	O
.	O
</s>
<s>
The	O
prefetch	O
procedure	O
tries	O
to	O
prefetch	O
data	O
from	O
NAND	O
to	O
SRAM	B-Architecture
so	O
that	O
the	O
hit	O
rate	O
of	O
the	O
NOR	O
access	O
is	O
high	O
over	O
SRAM	B-Architecture
.	O
</s>
<s>
If	O
pages	O
in	O
NAND	O
flash	O
could	O
be	O
prefetched	O
in	O
an	O
on-time	O
fashion	O
,	O
and	O
there	O
is	O
enough	O
SRAM	B-Architecture
space	O
for	O
caching	B-General_Concept
,	O
then	O
all	O
data	O
accesses	O
could	O
be	O
done	O
over	O
SRAM	B-Architecture
.	O
</s>
<s>
To	O
save	O
the	O
prediction	O
graph	O
over	O
flash	B-Device
memory	I-Device
with	O
overheads	O
(	O
SRAM	B-Architecture
capacity	O
)	O
minimized	O
,	O
the	O
subsequent	O
LBA	O
information	O
of	O
each	O
regular	O
node	O
is	O
saved	O
at	O
the	O
spare	O
area	O
of	O
the	O
corresponding	O
page	O
.	O
</s>
<s>
The	O
branch	O
table	O
can	O
be	O
saved	O
on	O
flash	B-Device
memory	I-Device
.	O
</s>
<s>
During	O
the	O
run	B-Library
time	I-Library
,	O
the	O
entire	O
table	O
can	O
be	O
loaded	O
into	O
SRAM	B-Architecture
for	O
better	O
performance	O
.	O
</s>
<s>
If	O
there	O
is	O
not	O
enough	O
SRAM	B-Architecture
space	O
,	O
parts	O
of	O
the	O
table	O
can	O
be	O
loaded	O
in	O
an	O
on-demand	O
fashion	O
.	O
</s>
<s>
The	O
objective	O
of	O
the	O
prefetch	O
procedure	O
is	O
to	O
prefetch	O
data	O
from	O
NAND	O
based	O
on	O
a	O
given	O
prediction	O
graph	O
such	O
that	O
most	O
data	O
accesses	O
occur	O
over	O
SRAM	B-Architecture
.	O
</s>
<s>
In	O
order	O
to	O
efficiently	O
look	O
up	O
a	O
selected	O
page	O
in	O
the	O
cache	B-General_Concept
,	O
a	O
cyclic	B-Data_Structure
queue	I-Data_Structure
is	O
adopted	O
in	O
the	O
cache	B-General_Concept
management	O
.	O
</s>
<s>
The	O
prefetch	O
procedure	O
is	O
done	O
in	O
a	O
greedy	B-Algorithm
way	O
:	O
Let	O
P1	O
be	O
the	O
last	O
prefetched	O
page	O
.	O
</s>
<s>
If	O
P1	O
corresponds	O
to	O
a	O
branch	O
node	O
,	O
then	O
the	O
procedure	O
should	O
prefetch	O
pages	O
by	O
following	O
all	O
possible	O
next	O
LBA	O
links	O
in	O
an	O
equal	O
base	O
and	O
a	O
round-robin	B-Algorithm
way	O
.	O
</s>
