<s>
M·CORE	B-Device
is	O
a	O
low-power	O
,	O
RISC-based	B-Architecture
microcontroller	B-Architecture
architecture	B-General_Concept
developed	O
by	O
Motorola	O
(	O
subsequently	O
Freescale	O
,	O
now	O
part	O
of	O
NXP	O
)	O
,	O
intended	O
for	O
use	O
in	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
Introduced	O
in	O
late	O
1997	O
,	O
the	O
architecture	B-General_Concept
combines	O
a	O
32-bit	O
internal	O
data	O
path	O
with	O
16-bit	B-Device
instructions	O
,	O
and	O
includes	O
a	O
four-stage	O
instruction	B-General_Concept
pipeline	I-General_Concept
.	O
</s>
<s>
M·CORE	B-Device
processors	O
employ	O
a	O
von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
with	O
shared	O
program	O
and	O
data	O
bus	O
—	O
executing	O
instructions	O
from	O
within	O
data	O
memory	O
is	O
possible	O
.	O
</s>
<s>
Motorola	O
engineers	O
designed	O
M·CORE	B-Device
to	O
have	O
low	O
power	O
consumption	O
and	O
high	O
code	O
density	O
.	O
</s>
