<s>
MyHDL	B-Language
is	O
a	O
Python-based	O
hardware	O
description	O
language	O
(	O
HDL	O
)	O
.	O
</s>
<s>
Features	O
of	O
MyHDL	B-Language
include	O
:	O
</s>
<s>
The	O
ability	O
to	O
generate	O
VHDL	B-Language
and	O
Verilog	B-Language
code	O
from	O
a	O
MyHDL	B-Language
design	O
.	O
</s>
<s>
The	O
ability	O
to	O
generate	O
a	O
testbench	O
(	O
Conversion	O
of	O
test	O
benches	O
)	O
with	O
test	O
vectors	O
in	O
VHDL	B-Language
or	O
Verilog	B-Language
,	O
based	O
on	O
complex	O
computations	O
in	O
Python	B-Language
.	O
</s>
<s>
The	O
ability	O
to	O
do	O
co-simulation	O
with	O
Verilog	B-Language
.	O
</s>
<s>
MyHDL	B-Language
's	O
translator	O
tool	O
automatically	O
writes	O
conversion	O
functions	O
when	O
the	O
target	O
language	O
requires	O
them	O
.	O
</s>
<s>
MyHDL	B-Language
is	O
developed	O
by	O
Jan	B-Language
Decaluwe	I-Language
.	O
</s>
<s>
Here	O
,	O
you	O
can	O
see	O
some	O
examples	O
of	O
conversions	O
from	O
MyHDL	B-Language
designs	O
to	O
VHDL	B-Language
and/or	O
Verilog	B-Language
.	O
</s>
<s>
You	O
can	O
create	O
an	O
instance	O
and	O
convert	O
to	O
Verilog	B-Language
and	O
VHDL	B-Language
as	O
follows	O
:	O
</s>
<s>
The	O
generated	O
Verilog	B-Language
code	O
looks	O
as	O
follows	O
:	O
</s>
<s>
The	O
generated	O
VHDL	B-Language
code	O
looks	O
as	O
follows	O
:	O
</s>
