<s>
A	O
multiprocessor	B-Operating_System
system	O
is	O
defined	O
as	O
"	O
a	O
system	O
with	O
more	O
than	O
one	O
processor	O
"	O
,	O
and	O
,	O
more	O
precisely	O
,	O
"	O
a	O
number	O
of	O
central	O
processing	O
units	O
linked	O
together	O
to	O
enable	O
parallel	B-Operating_System
processing	I-Operating_System
to	O
take	O
place	O
"	O
.	O
</s>
<s>
The	O
key	O
objective	O
of	O
a	O
multiprocessor	B-Operating_System
is	O
to	O
boost	O
a	O
system	O
's	O
execution	O
speed	O
.	O
</s>
<s>
The	O
term	O
"	O
multiprocessor	B-Operating_System
"	O
can	O
be	O
confused	O
with	O
the	O
term	O
"	O
multiprocessing	B-Operating_System
"	O
.	O
</s>
<s>
While	O
multiprocessing	B-Operating_System
is	O
a	O
type	O
of	O
processing	O
in	O
which	O
two	O
or	O
more	O
processors	O
work	O
together	O
to	O
execute	O
multiple	O
programs	O
simultaneously	O
,	O
multiprocessor	B-Operating_System
refers	O
to	O
a	O
hardware	O
architecture	O
that	O
allows	O
multiprocessing	B-Operating_System
.	O
</s>
<s>
Multiprocessor	B-Operating_System
systems	O
are	O
classified	O
according	O
to	O
how	O
processor	O
memory	O
access	O
is	O
handled	O
and	O
whether	O
system	O
processors	O
are	O
of	O
a	O
single	O
type	O
or	O
various	O
ones	O
.	O
</s>
<s>
There	O
are	O
many	O
types	O
of	O
multiprocessor	B-Operating_System
systems	O
:	O
</s>
<s>
In	O
loosely-coupled	O
multiprocessor	B-Operating_System
systems	O
,	O
each	O
processor	O
has	O
its	O
own	O
local	O
memory	O
,	O
input/output	B-General_Concept
(	O
I/O	B-General_Concept
)	O
channels	O
,	O
and	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
Processors	O
exchange	O
data	O
over	O
a	O
high-speed	O
communication	O
network	O
by	O
sending	O
messages	O
via	O
a	O
technique	O
known	O
as	O
"	O
message	B-Architecture
passing	I-Architecture
"	O
.	O
</s>
<s>
Loosely-coupled	O
multiprocessor	B-Operating_System
systems	O
are	O
also	O
known	O
as	O
distributed-memory	O
systems	O
,	O
as	O
the	O
processors	O
do	O
not	O
share	O
physical	O
memory	O
and	O
have	O
individual	O
I/O	B-General_Concept
channels	O
.	O
</s>
<s>
This	O
type	O
of	O
architecture	O
allows	O
parallel	B-Operating_System
processing	I-Operating_System
.	O
</s>
<s>
Multiprocessor	B-Operating_System
system	O
with	O
a	O
shared	O
memory	O
closely	O
connected	O
to	O
the	O
processors	O
.	O
</s>
<s>
A	O
symmetric	O
multiprocessing	B-Operating_System
system	O
is	O
a	O
system	O
with	O
centralized	O
shared	O
memory	O
called	O
main	O
memory	O
(	O
MM	O
)	O
operating	O
under	O
a	O
single	O
operating	B-General_Concept
system	I-General_Concept
with	O
two	O
or	O
more	O
homogeneous	O
processors	O
.	O
</s>
<s>
A	O
heterogeneous	B-Architecture
multiprocessing	I-Architecture
system	I-Architecture
contains	O
multiple	O
,	O
but	O
not	O
homogeneous	O
,	O
processing	O
units	O
–	O
central	O
processing	O
units	O
(	O
CPUs	O
)	O
,	O
graphics	O
processing	O
units	O
(	O
GPUs	O
)	O
,	O
digital	O
signal	O
processors	O
(	O
DSPs	O
)	O
,	O
or	O
any	O
type	O
of	O
application-specific	O
integrated	O
circuits	O
(	O
ASICs	O
)	O
.	O
</s>
<s>
Systems	O
operating	O
under	O
a	O
single	O
OS	O
(	O
operating	B-General_Concept
system	I-General_Concept
)	O
with	O
two	O
or	O
more	O
homogeneous	O
processors	O
and	O
with	O
a	O
centralized	O
shared	O
main	O
memory	O
.	O
</s>
<s>
A	O
symmetric	O
multiprocessor	B-Operating_System
system	O
(	O
SMP	O
)	O
is	O
a	O
system	O
with	O
a	O
pool	O
of	O
homogeneous	O
processors	O
running	O
under	O
a	O
single	O
OS	O
with	O
a	O
centralized	O
,	O
shared	O
main	O
memory	O
.	O
</s>
<s>
Each	O
processor	O
,	O
executing	O
different	O
programs	O
and	O
working	O
on	O
different	O
sets	O
of	O
data	O
,	O
has	O
the	O
ability	O
to	O
share	O
common	O
resources	O
(	O
memory	O
,	O
I/O	B-General_Concept
device	I-General_Concept
,	O
interrupt	O
system	O
,	O
and	O
so	O
on	O
)	O
that	O
are	O
connected	O
using	O
a	O
system	O
bus	O
,	O
a	O
crossbar	O
,	O
or	O
a	O
mix	O
of	O
the	O
two	O
,	O
or	O
an	O
address	O
bus	O
and	O
data	O
crossbar	O
.	O
</s>
<s>
To	O
overcome	O
this	O
limitation	O
,	O
the	O
architecture	O
called	O
"	O
cc-NUMA	B-Operating_System
"	O
(	O
cache	O
coherency	O
–	O
non-uniform	B-Operating_System
memory	I-Operating_System
access	I-Operating_System
)	O
is	O
normally	O
used	O
.	O
</s>
<s>
The	O
main	O
characteristic	O
of	O
a	O
cc-NUMA	B-Operating_System
system	O
is	O
having	O
shared	O
global	O
memory	O
that	O
is	O
distributed	O
to	O
each	O
node	O
,	O
although	O
the	O
effective	O
"	O
access	O
"	O
a	O
processor	O
has	O
to	O
the	O
memory	O
of	O
a	O
remote	O
component	O
subsystem	O
,	O
or	O
"	O
node	O
"	O
,	O
is	O
slower	O
compared	O
to	O
local	O
memory	O
access	O
,	O
which	O
is	O
why	O
the	O
memory	O
access	O
is	O
"	O
non-uniform	O
"	O
.	O
</s>
<s>
A	O
cc	O
–	O
NUMA	B-Operating_System
system	O
is	O
a	O
cluster	O
of	O
SMP	O
systems	O
–	O
each	O
called	O
a	O
"	O
node	O
"	O
,	O
which	O
can	O
have	O
a	O
single	O
processor	O
,	O
a	O
multi-core	O
processor	O
,	O
or	O
a	O
mix	O
of	O
the	O
two	O
,	O
of	O
one	O
or	O
other	O
kinds	O
of	O
architecture	O
–	O
connected	O
via	O
a	O
high-speed	O
"	O
connection	O
network	O
"	O
that	O
can	O
be	O
a	O
"	O
link	O
"	O
that	O
can	O
be	O
a	O
single	O
or	O
double-reverse	O
ring	O
,	O
or	O
multi-ring	O
,	O
point-to-point	O
connections	O
,	O
or	O
a	O
mix	O
of	O
these	O
(	O
e.g.	O
</s>
<s>
IBM	B-Device
Power	I-Device
Systems	I-Device
)	O
,	O
bus	O
interconnection	O
(	O
e.g.	O
</s>
<s>
NUMAq	O
)	O
,	O
"	O
crossbar	O
"	O
,	O
"	O
segmented	O
bus	O
"	O
(	O
NUMA	B-Operating_System
Bull	O
HN	O
ISI	O
ex	O
Honeywell	O
,	O
)	O
"	O
mesh	B-Architecture
router	I-Architecture
"	O
,	O
etc	O
.	O
</s>
<s>
cc-NUMA	B-Operating_System
is	O
also	O
called	O
"	O
distributed	O
shared	O
memory	O
"	O
(	O
DSM	O
)	O
architecture	O
.	O
</s>
<s>
With	O
this	O
solution	O
,	O
the	O
cc-NUMA	B-Operating_System
system	O
becomes	O
very	O
close	O
to	O
a	O
large	O
SMP	O
system	O
.	O
</s>
