<s>
A	O
multigate	B-Algorithm
device	I-Algorithm
,	O
multi-gate	B-Algorithm
MOSFET	I-Algorithm
or	O
multi-gate	B-Algorithm
field-effect	I-Algorithm
transistor	I-Algorithm
(	O
MuGFET	B-Algorithm
)	O
refers	O
to	O
a	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
field-effect	I-Architecture
transistor	I-Architecture
(	O
MOSFET	B-Architecture
)	O
that	O
has	O
more	O
than	O
one	O
gate	O
on	O
a	O
single	O
transistor	B-Application
.	O
</s>
<s>
A	O
multigate	B-Algorithm
device	I-Algorithm
employing	O
independent	O
gate	O
electrodes	O
is	O
sometimes	O
called	O
a	O
multiple-independent-gate	B-Algorithm
field-effect	I-Algorithm
transistor	I-Algorithm
(	O
MIGFET	B-Algorithm
)	O
.	O
</s>
<s>
The	O
most	O
widely	O
used	O
multi-gate	B-Algorithm
devices	O
are	O
the	O
FinFET	O
(	O
fin	O
field-effect	O
transistor	B-Application
)	O
and	O
the	O
GAAFET	O
(	O
gate-all-around	O
field-effect	O
transistor	B-Application
)	O
,	O
which	O
are	O
non-planar	O
transistors	B-Application
,	O
or	O
3D	B-Algorithm
transistors	I-Algorithm
.	O
</s>
<s>
Multi-gate	B-Algorithm
transistors	B-Application
are	O
one	O
of	O
the	O
several	O
strategies	O
being	O
developed	O
by	O
MOS	B-Architecture
semiconductor	O
manufacturers	O
to	O
create	O
ever-smaller	O
microprocessors	B-Architecture
and	O
memory	B-Algorithm
cells	I-Algorithm
,	O
colloquially	O
referred	O
to	O
as	O
extending	O
Moore	O
's	O
law	O
(	O
in	O
its	O
narrow	O
,	O
specific	O
version	O
concerning	O
density	O
scaling	O
,	O
exclusive	O
of	O
its	O
careless	O
historical	O
conflation	O
with	O
Dennard	O
scaling	O
)	O
.	O
</s>
<s>
Development	O
efforts	O
into	O
multigate	B-Algorithm
transistors	I-Algorithm
have	O
been	O
reported	O
by	O
the	O
Electrotechnical	O
Laboratory	O
,	O
Toshiba	O
,	O
Grenoble	O
INP	O
,	O
Hitachi	O
,	O
IBM	O
,	O
TSMC	O
,	O
UC	O
Berkeley	O
,	O
Infineon	O
Technologies	O
,	O
Intel	O
,	O
AMD	O
,	O
Samsung	B-Application
Electronics	O
,	O
KAIST	O
,	O
Freescale	O
Semiconductor	O
,	O
and	O
others	O
,	O
and	O
the	O
ITRS	O
predicted	O
correctly	O
that	O
such	O
devices	O
will	O
be	O
the	O
cornerstone	O
of	O
sub-32	O
nm	O
technologies	O
.	O
</s>
<s>
The	O
primary	O
roadblock	O
to	O
widespread	O
implementation	O
is	O
manufacturability	O
,	O
as	O
both	O
planar	B-Algorithm
and	O
non-planar	O
designs	O
present	O
significant	O
challenges	O
,	O
especially	O
with	O
respect	O
to	O
lithography	B-Algorithm
and	O
patterning	O
.	O
</s>
<s>
Other	O
complementary	O
strategies	O
for	O
device	O
scaling	O
include	O
channel	O
strain	O
engineering	O
,	O
silicon-on-insulator-based	O
technologies	O
,	O
and	O
high-κ/metal	O
gate	O
materials	O
.	O
</s>
<s>
Dual-gate	B-Algorithm
MOSFETs	I-Algorithm
are	O
commonly	O
used	O
in	O
very	B-Algorithm
high	I-Algorithm
frequency	I-Algorithm
(	O
VHF	B-Algorithm
)	O
mixers	O
and	O
in	O
sensitive	O
VHF	B-Algorithm
front-end	O
amplifiers	O
.	O
</s>
<s>
Dozens	O
of	O
multigate	B-Algorithm
transistor	I-Algorithm
variants	O
may	O
be	O
found	O
in	O
the	O
literature	O
.	O
</s>
<s>
In	O
general	O
,	O
these	O
variants	O
may	O
be	O
differentiated	O
and	O
classified	O
in	O
terms	O
of	O
architecture	O
(	O
planar	B-Algorithm
vs.	O
non-planar	O
design	O
)	O
and	O
the	O
number	O
of	O
channels/gates	O
(	O
2	O
,	O
3	O
,	O
or	O
4	O
)	O
.	O
</s>
<s>
A	O
planar	B-Algorithm
double-gate	B-Algorithm
MOSFET	B-Architecture
(	O
DGMOS	O
)	O
employs	O
conventional	O
planar	B-Algorithm
(	O
layer-by-layer	O
)	O
manufacturing	B-Architecture
processes	B-Algorithm
to	O
create	O
double-gate	B-Algorithm
MOSFET	B-Architecture
(	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
field-effect	I-Architecture
transistor	I-Architecture
)	O
devices	O
,	O
avoiding	O
more	O
stringent	O
lithography	B-Algorithm
requirements	O
associated	O
with	O
non-planar	O
,	O
vertical	O
transistor	B-Application
structures	O
.	O
</s>
<s>
In	O
planar	B-Algorithm
double-gate	B-Algorithm
transistors	I-Algorithm
the	O
drain	O
–	O
source	O
channel	O
is	O
sandwiched	O
between	O
two	O
independently	O
fabricated	B-Architecture
gate/gate	O
-oxide	O
stacks	O
.	O
</s>
<s>
FlexFET	O
is	O
a	O
planar	B-Algorithm
,	O
independently	O
double-gated	B-Algorithm
transistor	B-Application
with	O
a	O
damascene	O
metal	O
top	O
gate	O
MOSFET	B-Architecture
and	O
an	O
implanted	O
JFET	O
bottom	O
gate	O
that	O
are	O
self-aligned	O
in	O
a	O
gate	O
trench	O
.	O
</s>
<s>
FlexFET	O
is	O
a	O
true	O
double-gate	B-Algorithm
transistor	I-Algorithm
in	O
that	O
(	O
1	O
)	O
both	O
the	O
top	O
and	O
bottom	O
gates	O
provide	O
transistor	B-Application
operation	O
,	O
and	O
(	O
2	O
)	O
the	O
operation	O
of	O
the	O
gates	O
is	O
coupled	O
such	O
that	O
the	O
top	O
gate	O
operation	O
affects	O
the	O
bottom	O
gate	O
operation	O
and	O
vice	O
versa	O
.	O
</s>
<s>
FinFET	O
(	O
fin	O
field-effect	O
transistor	B-Application
)	O
is	O
a	O
type	O
of	O
non-planar	O
transistor	B-Application
,	O
or	O
"	O
3D	O
"	O
transistor	B-Application
(	O
not	O
to	O
be	O
confused	O
with	O
3D	B-Architecture
microchips	I-Architecture
)	O
.	O
</s>
<s>
The	O
FinFET	O
is	O
a	O
variation	O
on	O
traditional	O
MOSFETs	B-Architecture
distinguished	O
by	O
the	O
presence	O
of	O
a	O
thin	O
silicon	O
"	O
fin	O
"	O
inversion	O
channel	O
on	O
top	O
of	O
the	O
substrate	B-Architecture
,	O
allowing	O
the	O
gate	O
to	O
make	O
two	O
points	O
of	O
contact	O
:	O
the	O
left	O
and	O
right	O
sides	O
of	O
the	O
fin	O
.	O
</s>
<s>
The	O
first	O
FinFET	O
transistor	B-Application
type	O
was	O
called	O
a	O
"	O
Depleted	O
Lean-channel	O
Transistor	B-Application
"	O
or	O
"	O
DELTA	O
"	O
transistor	B-Application
,	O
which	O
was	O
first	O
fabricated	B-Architecture
by	O
Hitachi	O
Central	O
Research	O
Laboratory	O
's	O
Digh	O
Hisamoto	O
,	O
Toru	O
Kaga	O
,	O
Yoshifumi	O
Kawamoto	O
and	O
Eiji	O
Takeda	O
in	O
1989	O
.	O
</s>
<s>
In	O
1998	O
,	O
the	O
team	O
developed	O
the	O
first	O
N-channel	O
FinFETs	O
and	O
successfully	O
fabricated	B-Architecture
devices	O
down	O
to	O
a	O
17nm	O
process	O
.	O
</s>
<s>
They	O
coined	O
the	O
term	O
"	O
FinFET	O
"	O
(	O
fin	O
field-effect	O
transistor	B-Application
)	O
in	O
a	O
December	O
2000	O
paper	O
.	O
</s>
<s>
Among	O
microprocessor	B-Architecture
manufacturers	O
,	O
AMD	O
,	O
IBM	O
,	O
and	O
Freescale	O
describe	O
their	O
double-gate	B-Algorithm
development	O
efforts	O
as	O
FinFET	O
development	O
,	O
whereas	O
Intel	O
avoids	O
using	O
the	O
term	O
when	O
describing	O
their	O
closely	O
related	O
tri-gate	O
architecture	O
.	O
</s>
<s>
In	O
the	O
technical	O
literature	O
,	O
FinFET	O
is	O
used	O
somewhat	O
generically	O
to	O
describe	O
any	O
fin-based	O
,	O
multigate	B-Algorithm
transistor	I-Algorithm
architecture	O
regardless	O
of	O
number	O
of	O
gates	O
.	O
</s>
<s>
It	O
is	O
common	O
for	O
a	O
single	O
FinFET	O
transistor	B-Application
to	O
contain	O
several	O
fins	O
,	O
arranged	O
side	O
by	O
side	O
and	O
all	O
covered	O
by	O
the	O
same	O
gate	O
,	O
that	O
act	O
electrically	O
as	O
one	O
,	O
to	O
increase	O
drive	O
strength	O
and	O
performance	O
.	O
</s>
<s>
A	O
25nm	O
transistor	B-Application
operating	O
on	O
just	O
0.7volt	O
was	O
demonstrated	O
in	O
December	O
2002	O
by	O
TSMC	O
(	O
Taiwan	O
Semiconductor	B-Architecture
Manufacturing	I-Architecture
Company	O
)	O
.	O
</s>
<s>
The	O
"	O
Omega	B-General_Concept
FinFET	O
"	O
design	O
is	O
named	O
after	O
the	O
similarity	O
between	O
the	O
Greek	O
letter	O
omega	B-General_Concept
( Ω	O
)	O
and	O
the	O
shape	O
in	O
which	O
the	O
gate	O
wraps	O
around	O
the	O
source/drain	O
structure	O
.	O
</s>
<s>
It	O
has	O
a	O
gate	O
delay	O
of	O
just	O
0.39picosecond	O
(	O
ps	O
)	O
for	O
the	O
N-type	O
transistor	B-Application
and	O
0.88ps	O
for	O
the	O
P-type	O
.	O
</s>
<s>
In	O
2004	O
,	O
Samsung	B-Application
Electronics	O
demonstrated	O
a	O
"	O
Bulk	O
FinFET	O
"	O
design	O
,	O
which	O
made	O
it	O
possible	O
to	O
mass-produce	O
FinFET	O
devices	O
.	O
</s>
<s>
They	O
demonstrated	O
dynamic	O
random-access	B-Architecture
memory	I-Architecture
(	O
DRAM	O
)	O
manufactured	O
with	O
a	O
90nm	O
Bulk	O
FinFET	O
process	O
.	O
</s>
<s>
In	O
2006	O
,	O
a	O
team	O
of	O
Korean	O
researchers	O
from	O
the	O
Korea	O
Advanced	O
Institute	O
of	O
Science	O
and	O
Technology	O
(	O
KAIST	O
)	O
and	O
the	O
National	O
Nano	O
Fab	O
Center	O
developed	O
a	O
3	O
nm	O
transistor	B-Application
,	O
the	O
world	O
's	O
smallest	O
nanoelectronic	B-Algorithm
device	O
,	O
based	O
on	O
FinFET	O
technology	O
.	O
</s>
<s>
In	O
September	O
2012	O
,	O
GlobalFoundries	O
announced	O
plans	O
to	O
offer	O
a	O
14-nanometer	O
process	O
technology	O
featuring	O
FinFET	O
three-dimensional	O
transistors	B-Application
in	O
2014	O
.	O
</s>
<s>
In	O
March	O
2014	O
,	O
TSMC	O
announced	O
that	O
it	O
is	O
nearing	O
implementation	O
of	O
several	O
16	O
nm	O
FinFETs	O
die-on	O
wafers	B-Architecture
manufacturing	B-Architecture
processes	B-Algorithm
:	O
</s>
<s>
In	O
March	O
2017	O
,	O
Samsung	B-Application
and	O
eSilicon	O
announced	O
the	O
tapeout	O
for	O
production	O
of	O
a	O
14nm	O
FinFET	O
ASIC	O
in	O
a	O
2.5D	O
package	O
.	O
</s>
<s>
A	O
tri-gate	O
transistor	B-Application
,	O
also	O
known	O
as	O
a	O
triple-gate	O
transistor	B-Application
,	O
is	O
a	O
type	O
of	O
MOSFET	B-Architecture
with	O
a	O
gate	O
on	O
three	O
of	O
its	O
sides	O
.	O
</s>
<s>
A	O
triple-gate	O
transistor	B-Application
was	O
first	O
demonstrated	O
in	O
1987	O
,	O
by	O
a	O
Toshiba	O
research	O
team	O
including	O
K	O
.	O
Hieda	O
,	O
Fumio	O
Horiguchi	O
and	O
H	O
.	O
Watanabe	O
.	O
</s>
<s>
They	O
realized	O
that	O
the	O
fully	O
depleted	O
(	O
FD	O
)	O
body	O
of	O
a	O
narrow	O
bulk	O
Si-based	O
transistor	B-Application
helped	O
improve	O
switching	O
due	O
to	O
a	O
lessened	O
body-bias	O
effect	O
.	O
</s>
<s>
In	O
1992	O
,	O
a	O
triple-gate	O
MOSFET	B-Architecture
was	O
demonstrated	O
by	O
IBM	O
researcher	O
Hon-Sum	O
Wong	O
.	O
</s>
<s>
Tri-gate	O
fabrication	B-Architecture
is	O
used	O
by	O
Intel	O
for	O
the	O
non-planar	O
transistor	B-Application
architecture	O
used	O
in	O
Ivy	B-Device
Bridge	I-Device
,	O
Haswell	B-Device
and	O
Skylake	B-Architecture
processors	O
.	O
</s>
<s>
These	O
transistors	B-Application
employ	O
a	O
single	O
gate	O
stacked	O
on	O
top	O
of	O
two	O
vertical	O
gates	O
(	O
a	O
single	O
gate	O
wrapped	O
over	O
three	O
sides	O
of	O
the	O
channel	O
)	O
,	O
allowing	O
essentially	O
three	O
times	O
the	O
surface	O
area	O
for	O
electrons	O
to	O
travel	O
.	O
</s>
<s>
Intel	O
reports	O
that	O
their	O
tri-gate	O
transistors	B-Application
reduce	O
leakage	O
and	O
consume	O
far	O
less	O
power	O
than	O
current	O
transistors	B-Application
.	O
</s>
<s>
This	O
allows	O
up	O
to	O
37%	O
higher	O
speed	O
or	O
a	O
power	O
consumption	O
at	O
under	O
50%	O
of	O
the	O
previous	O
type	O
of	O
transistors	B-Application
used	O
by	O
Intel	O
.	O
</s>
<s>
Intel	O
explains	O
:	O
"	O
The	O
additional	O
control	O
enables	O
as	O
much	O
transistor	B-Application
current	O
flowing	O
as	O
possible	O
when	O
the	O
transistor	B-Application
is	O
in	O
the	O
'	O
on	O
 '	O
state	O
(	O
for	O
performance	O
)	O
,	O
and	O
as	O
close	O
to	O
zero	O
as	O
possible	O
when	O
it	O
is	O
in	O
the	O
'	O
off	O
 '	O
state	O
(	O
to	O
minimize	O
power	O
)	O
,	O
and	O
enables	O
the	O
transistor	B-Application
to	O
switch	O
very	O
quickly	O
between	O
the	O
two	O
states	O
(	O
again	O
,	O
for	O
performance	O
)	O
.	O
"	O
</s>
<s>
Intel	O
announced	O
"	O
triple-gate	O
transistors	B-Application
"	O
which	O
maximize	O
"	O
transistor	B-Application
switching	O
performance	O
and	O
decreases	O
power-wasting	O
leakage	O
"	O
.	O
</s>
<s>
No	O
further	O
announcements	O
of	O
this	O
technology	O
were	O
made	O
until	O
Intel	O
's	O
announcement	O
in	O
May	O
2011	O
,	O
although	O
it	O
was	O
stated	O
at	O
IDF	O
2011	O
,	O
that	O
they	O
demonstrated	O
a	O
working	O
SRAM	B-Architecture
chip	O
based	O
on	O
this	O
technology	O
at	O
IDF	O
2009	O
.	O
</s>
<s>
On	O
April	O
23	O
,	O
2012	O
,	O
Intel	O
released	O
a	O
new	O
line	O
of	O
CPUs	O
,	O
termed	O
Ivy	B-Device
Bridge	I-Device
,	O
which	O
feature	O
tri-gate	O
transistors	B-Application
.	O
</s>
<s>
The	O
new	O
style	O
of	O
transistor	B-Application
was	O
described	O
on	O
May	O
4	O
,	O
2011	O
,	O
in	O
San	O
Francisco	O
.	O
</s>
<s>
Intel	O
factories	O
are	O
expected	O
to	O
make	O
upgrades	O
over	O
2011	O
and	O
2012	O
to	O
be	O
able	O
to	O
manufacture	O
the	O
Ivy	B-Device
Bridge	I-Device
CPUs	O
.	O
</s>
<s>
As	O
well	O
as	O
being	O
used	O
in	O
Intel	O
's	O
Ivy	B-Device
Bridge	I-Device
chips	O
for	O
desktop	O
PCs	O
,	O
the	O
new	O
transistors	B-Application
will	O
also	O
be	O
used	O
in	O
Intel	O
's	O
Atom	B-Device
chips	I-Device
for	O
low-powered	O
devices	O
.	O
</s>
<s>
A	O
gate-all-around	O
(	O
GAA	O
)	O
FET	O
,	O
abbreviated	O
GAAFET	O
,	O
and	O
also	O
known	O
as	O
a	O
surrounding-gate	O
transistor	B-Application
(	O
SGT	O
)	O
,	O
is	O
similar	O
in	O
concept	O
to	O
a	O
FinFET	O
except	O
that	O
the	O
gate	O
material	O
surrounds	O
the	O
channel	O
region	O
on	O
all	O
sides	O
.	O
</s>
<s>
They	O
have	O
also	O
been	O
successfully	O
etched	O
onto	O
InGaAs	O
nanowires	B-Architecture
,	O
which	O
have	O
a	O
higher	O
electron	O
mobility	O
than	O
silicon	O
.	O
</s>
<s>
A	O
gate-all-around	O
(	O
GAA	O
)	O
MOSFET	B-Architecture
was	O
first	O
demonstrated	O
in	O
1988	O
,	O
by	O
a	O
Toshiba	O
research	O
team	O
including	O
Fujio	O
Masuoka	O
,	O
Hiroshi	O
Takato	O
,	O
and	O
Kazumasa	O
Sunouchi	O
,	O
who	O
demonstrated	O
a	O
vertical	O
nanowire	B-Architecture
GAAFET	O
which	O
they	O
called	O
a	O
"	O
surrounding	O
gate	O
transistor	B-Application
"	O
(	O
SGT	O
)	O
.	O
</s>
<s>
Masuoka	O
,	O
best	O
known	O
as	O
the	O
inventor	O
of	O
flash	B-Device
memory	I-Device
,	O
later	O
left	O
Toshiba	O
and	O
founded	O
Unisantis	O
Electronics	O
in	O
2004	O
to	O
research	O
surrounding-gate	O
technology	O
along	O
with	O
Tohoku	O
University	O
.	O
</s>
<s>
In	O
2006	O
,	O
a	O
team	O
of	O
Korean	O
researchers	O
from	O
the	O
Korea	O
Advanced	O
Institute	O
of	O
Science	O
and	O
Technology	O
(	O
KAIST	O
)	O
and	O
the	O
National	O
Nano	O
Fab	O
Center	O
developed	O
a	O
3	O
nm	O
transistor	B-Application
,	O
the	O
world	O
's	O
smallest	O
nanoelectronic	B-Algorithm
device	O
,	O
based	O
on	O
gate-all-around	O
(	O
GAA	O
)	O
FinFET	O
technology	O
.	O
</s>
<s>
GAAFET	O
transistors	B-Application
may	O
make	O
use	O
of	O
high-k/metal	O
gate	O
materials	O
.	O
</s>
<s>
They	O
were	O
used	O
by	O
IBM	O
to	O
demonstrate	O
5	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
technology	O
.	O
</s>
<s>
As	O
of	O
2020	O
,	O
Samsung	B-Application
and	O
Intel	O
have	O
announced	O
plans	O
to	O
mass	O
produce	O
GAAFET	O
transistors	B-Application
(	O
specifically	O
MBCFET	O
transistors	B-Application
)	O
while	O
TSMC	O
has	O
announced	O
that	O
they	O
will	O
continue	O
to	O
use	O
FinFETs	O
in	O
their	O
3nm	B-Algorithm
node	O
,	O
despite	O
TSMC	O
developing	O
GAAFET	O
transistors	B-Application
.	O
</s>
<s>
A	O
multi-bridge	O
channel	O
FET	O
(	O
MBCFET	O
)	O
is	O
similar	O
to	O
a	O
GAAFET	O
except	O
for	O
the	O
use	O
of	O
nanosheets	O
instead	O
of	O
nanowires	B-Architecture
.	O
</s>
<s>
MBCFET	O
is	O
a	O
word	O
mark	O
(	O
trademark	O
)	O
registered	O
in	O
the	O
U.S.	O
to	O
Samsung	B-Application
Electronics	O
.	O
</s>
<s>
Samsung	B-Application
plans	O
on	O
mass	O
producing	O
MBCFET	O
transistors	B-Application
at	O
the	O
3	B-Algorithm
nm	I-Algorithm
node	O
for	O
its	O
foundry	O
customers	O
.	O
</s>
<s>
Intel	O
is	O
also	O
developing	O
RibbonFET	O
,	O
a	O
variation	O
of	O
MBCFET	O
"	O
nanoribbon	O
"	O
transistors	B-Application
.	O
</s>
<s>
Planar	B-Algorithm
transistors	B-Application
have	O
been	O
the	O
core	O
of	O
integrated	O
circuits	O
for	O
several	O
decades	O
,	O
during	O
which	O
the	O
size	O
of	O
the	O
individual	O
transistors	B-Application
has	O
steadily	O
decreased	O
.	O
</s>
<s>
As	O
the	O
size	O
decreases	O
,	O
planar	B-Algorithm
transistors	B-Application
increasingly	O
suffer	O
from	O
the	O
undesirable	O
short-channel	O
effect	O
,	O
especially	O
"	O
off-state	O
"	O
leakage	O
current	O
,	O
which	O
increases	O
the	O
idle	O
power	O
required	O
by	O
the	O
device	O
.	O
</s>
<s>
In	O
a	O
multigate	B-Algorithm
device	I-Algorithm
,	O
the	O
channel	O
is	O
surrounded	O
by	O
several	O
gates	O
on	O
multiple	O
surfaces	O
.	O
</s>
<s>
Multigate	B-Algorithm
transistors	I-Algorithm
also	O
provide	O
a	O
better	O
analog	O
performance	O
due	O
to	O
a	O
higher	O
intrinsic	O
gain	O
and	O
lower	O
channel	O
length	O
modulation	O
.	O
</s>
<s>
Nonplanar	O
devices	O
are	O
also	O
more	O
compact	O
than	O
conventional	O
planar	B-Algorithm
transistors	B-Application
,	O
enabling	O
higher	O
transistor	B-Application
density	O
which	O
translates	O
to	O
smaller	O
overall	O
microelectronics	O
.	O
</s>
<s>
The	O
primary	O
challenges	O
to	O
integrating	O
nonplanar	O
multigate	B-Algorithm
devices	I-Algorithm
into	O
conventional	O
semiconductor	B-Architecture
manufacturing	I-Architecture
processes	I-Architecture
include	O
:	O
</s>
<s>
BSIMCMG106.0.0	O
,	O
officially	O
released	O
on	O
March	O
1	O
,	O
2012	O
by	O
UC	O
Berkeley	O
BSIM	B-Algorithm
Group	I-Algorithm
,	O
is	O
the	O
first	O
standard	O
model	O
for	O
FinFETs	O
.	O
</s>
<s>
BSIM-CMG	O
is	O
implemented	O
in	O
Verilog-A	B-Language
.	O
</s>
<s>
All	O
of	O
the	O
important	O
multi-gate	B-Algorithm
(	O
MG	O
)	O
transistor	B-Application
behavior	O
is	O
captured	O
by	O
this	O
model	O
.	O
</s>
<s>
Analysis	O
of	O
electrostatic	O
potential	O
in	O
the	O
body	O
of	O
MG	O
MOSFETs	B-Architecture
provided	O
a	O
model	O
equation	O
for	O
short-channel	O
effects	O
(	O
SCE	O
)	O
.	O
</s>
