<s>
Digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
(	O
DSP	O
)	O
is	O
a	O
ubiquitous	O
methodology	O
in	O
scientific	O
and	O
engineering	O
computations	O
.	O
</s>
<s>
Modern	O
general	O
purpose	O
graphics	B-Architecture
processing	I-Architecture
units	I-Architecture
(	O
GPGPUs	B-Architecture
)	O
have	O
an	O
excellent	O
throughput	O
on	O
vector	O
operations	O
and	O
numeric	O
manipulations	O
through	O
a	O
high	O
degree	O
of	O
parallel	O
computations	O
.	O
</s>
<s>
Processing	O
digital	O
signals	O
,	O
particularly	O
multidimensional	O
signals	O
,	O
often	O
involves	O
a	O
series	O
of	O
vector	O
operations	O
on	O
massive	O
numbers	O
of	O
independent	O
data	O
samples	O
,	O
GPGPUs	B-Architecture
are	O
now	O
widely	O
employed	O
to	O
accelerate	O
multidimensional	O
DSP	O
,	O
such	O
as	O
image	B-Algorithm
processing	I-Algorithm
,	O
video	O
codecs	O
,	O
radar	B-Algorithm
signal	I-Algorithm
analysis	I-Algorithm
,	O
sonar	O
signal	O
processing	O
,	O
and	O
ultrasound	B-Application
scanning	I-Application
.	O
</s>
<s>
Conceptually	O
,	O
GPGPUs	B-Architecture
dramatically	O
reduce	O
the	O
computation	O
complexity	O
when	O
compared	O
with	O
central	O
processing	O
units	O
(	O
CPUs	B-Device
)	O
,	O
digital	B-Architecture
signal	I-Architecture
processors	I-Architecture
(	O
DSPs	O
)	O
,	O
or	O
other	O
FPGA	B-Architecture
accelerators	O
.	O
</s>
<s>
Therefore	O
,	O
it	O
is	O
still	O
hard	O
to	O
obtain	O
the	O
desired	O
computation	O
results	O
with	O
digital	B-Architecture
signal	I-Architecture
processors	I-Architecture
(	O
DSPs	O
)	O
.	O
</s>
<s>
Digital	B-Architecture
signal	I-Architecture
processors	I-Architecture
are	O
designed	O
specifically	O
to	O
process	O
vector	O
operations	O
.	O
</s>
<s>
However	O
,	O
most	O
digital	B-Architecture
signal	I-Architecture
processors	I-Architecture
are	O
only	O
capable	O
of	O
manipulating	O
a	O
few	O
operations	O
in	O
parallel	O
.	O
</s>
<s>
This	O
kind	O
of	O
design	O
is	O
sufficient	O
to	O
accelerate	O
audio	O
processing	O
(	O
1-D	O
signals	O
)	O
and	O
image	B-Algorithm
processing	I-Algorithm
(	O
2-D	O
signals	O
)	O
.	O
</s>
<s>
In	O
order	O
to	O
accelerate	O
multidimensional	O
DSP	O
computations	O
,	O
using	O
dedicated	O
supercomputers	B-Architecture
or	O
cluster	B-Architecture
computers	I-Architecture
is	O
required	O
in	O
some	O
circumstances	O
,	O
e.g.	O
,	O
weather	O
forecasting	O
and	O
military	O
radars	O
.	O
</s>
<s>
Nevertheless	O
,	O
using	O
supercomputers	B-Architecture
designated	O
to	O
simply	O
perform	O
DSP	O
operations	O
takes	O
considerable	O
money	O
cost	O
and	O
energy	O
consumption	O
.	O
</s>
<s>
GPUs	B-Architecture
are	O
originally	O
devised	O
to	O
accelerate	O
image	B-Algorithm
processing	I-Algorithm
and	O
video	O
stream	O
rendering	O
.	O
</s>
<s>
Moreover	O
,	O
since	O
modern	O
GPUs	B-Architecture
have	O
good	O
ability	O
to	O
perform	O
numeric	O
computations	O
in	O
parallel	O
with	O
a	O
relatively	O
low	O
cost	O
and	O
better	O
energy	O
efficiency	O
,	O
GPUs	B-Architecture
are	O
becoming	O
a	O
popular	O
alternative	O
to	O
replace	O
supercomputers	B-Architecture
performing	O
multidimensional	O
DSP	O
.	O
</s>
<s>
Modern	O
GPU	B-Architecture
designs	O
are	O
mainly	O
based	O
on	O
the	O
SIMD	B-Device
(	O
Single	B-Device
Instruction	I-Device
Multiple	I-Device
Data	I-Device
)	O
computation	O
paradigm	O
.	O
</s>
<s>
This	O
type	O
of	O
GPU	B-Architecture
devices	O
is	O
so-called	O
general-purpose	O
GPUs	B-Architecture
(	O
GPGPUs	B-Architecture
)	O
.	O
</s>
<s>
GPGPUs	B-Architecture
are	O
able	O
to	O
perform	O
an	O
operation	O
on	O
multiple	O
independent	O
data	O
concurrently	O
with	O
their	O
vector	O
or	O
SIMD	B-Device
functional	O
units	O
.	O
</s>
<s>
A	O
modern	O
GPGPU	B-Architecture
can	O
spawn	O
thousands	O
of	O
concurrent	O
threads	O
and	O
process	O
all	O
threads	O
in	O
a	O
batch	O
manner	O
.	O
</s>
<s>
With	O
this	O
nature	O
,	O
GPGPUs	B-Architecture
can	O
be	O
employed	O
as	O
DSP	O
accelerators	O
easily	O
while	O
many	O
DSP	O
problems	O
can	O
be	O
solved	O
by	O
divide-and-conquer	B-Algorithm
algorithms	I-Algorithm
.	O
</s>
<s>
For	O
example	O
,	O
multiplying	O
two	O
matrices	O
can	O
be	O
processed	O
by	O
concurrent	O
threads	O
on	O
a	O
GPGPU	B-Architecture
device	O
without	O
any	O
output	O
data	O
dependency	O
.	O
</s>
<s>
Therefore	O
,	O
theoretically	O
,	O
by	O
means	O
of	O
GPGPU	B-Architecture
acceleration	O
,	O
we	O
can	O
gain	O
up	O
to	O
speedup	O
compared	O
with	O
a	O
traditional	O
CPU	B-Device
or	O
digital	B-Architecture
signal	I-Architecture
processor	I-Architecture
.	O
</s>
<s>
Currently	O
,	O
there	O
are	O
several	O
existing	O
programming	O
languages	O
or	O
interfaces	O
which	O
support	O
GPGPU	B-Architecture
programming	O
.	O
</s>
<s>
CUDA	B-Architecture
is	O
the	O
standard	O
interface	O
to	O
program	O
NVIDIA	O
GPUs	B-Architecture
.	O
</s>
<s>
NVIDIA	O
also	O
provides	O
many	O
CUDA	B-Architecture
libraries	O
to	O
support	O
DSP	O
acceleration	O
on	O
NVIDIA	O
GPU	B-Architecture
devices	O
.	O
</s>
<s>
OpenCL	B-Application
is	O
an	O
industrial	O
standard	O
which	O
was	O
originally	O
proposed	O
by	O
Apple	O
Inc	O
.	O
and	O
is	O
maintained	O
and	O
developed	O
by	O
the	B-Library
Khronos	I-Library
Group	I-Library
now	O
.	O
</s>
<s>
OpenCL	B-Application
provides	O
C++	B-Language
like	O
APIs	B-Application
for	O
programming	O
different	O
devices	O
universally	O
,	O
including	O
GPGPUs	B-Architecture
.	O
</s>
<s>
The	O
following	O
figure	O
illustrates	O
the	O
execution	O
flow	O
of	O
launching	O
an	O
OpenCL	B-Application
program	O
on	O
a	O
GPU	B-Architecture
device	O
.	O
</s>
<s>
The	O
CPU	B-Device
first	O
detects	O
OpenCL	B-Application
devices	O
(	O
GPU	B-Architecture
in	O
this	O
case	O
)	O
and	O
than	O
invokes	O
a	O
just-in-time	O
compiler	O
to	O
translate	O
the	O
OpenCL	B-Application
source	O
code	O
into	O
target	O
binary	O
.	O
</s>
<s>
CPU	B-Device
then	O
sends	O
data	O
to	O
GPU	B-Architecture
to	O
perform	O
computations	O
.	O
</s>
<s>
When	O
the	O
GPU	B-Architecture
is	O
processing	O
data	O
,	O
CPU	B-Device
is	O
free	O
to	O
process	O
its	O
own	O
tasks	O
.	O
</s>
<s>
C++	B-Language
AMP	I-Language
is	O
a	O
programming	O
model	O
proposed	O
by	O
Microsoft	O
.	O
</s>
<s>
OpenACC	B-Operating_System
is	O
a	O
programming	O
standard	O
for	O
parallel	O
computing	O
developed	O
by	O
Cray	O
,	O
CAPS	O
,	O
NVIDIA	O
and	O
PGI	O
.	O
</s>
<s>
OpenAcc	B-Operating_System
targets	O
programming	O
for	O
CPU	B-Device
and	O
GPU	B-Architecture
heterogeneous	O
systems	O
with	O
C	B-Language
,	O
C++	B-Language
,	O
and	O
Fortran	B-Application
extensions	O
.	O
</s>
<s>
Therefore	O
,	O
with	O
a	O
CPU	B-Device
implementation	O
,	O
the	O
time	O
complexity	O
to	O
achieve	O
this	O
computation	O
is	O
Θ(n3 )	O
in	O
the	O
following	O
C	B-Language
example	O
.	O
</s>
<s>
Hence	O
,	O
the	O
computation	O
can	O
be	O
fully	O
parallelized	O
by	O
SIMD	B-Device
processors	O
,	O
such	O
as	O
GPGPU	B-Architecture
devices	O
.	O
</s>
<s>
With	O
a	O
GPGPU	B-Architecture
implementation	O
,	O
the	O
time	O
complexity	O
significantly	O
reduces	O
to	O
Θ(n )	O
by	O
unrolling	O
the	O
for-loop	O
as	O
shown	O
in	O
the	O
following	O
OpenCL	B-Application
example	O
.	O
</s>
<s>
As	O
the	O
following	O
OpenCL	B-Application
example	O
shows	O
,	O
with	O
GPGPU	B-Architecture
acceleration	O
,	O
the	O
total	O
computation	O
time	O
effectively	O
decreases	O
to	O
Θ(n2 )	O
since	O
all	O
output	O
elements	O
are	O
data	O
independent	O
.	O
</s>
<s>
Overall	O
,	O
for	O
a	O
s-D	O
convolution	O
,	O
a	O
GPGPU	B-Architecture
implementation	O
has	O
time	O
complexity	O
Θ(ns )	O
,	O
whereas	O
a	O
CPU	B-Device
implementation	O
has	O
time	O
complexity	O
Θ(n2s )	O
.	O
</s>
<s>
In	O
addition	O
to	O
convolution	O
,	O
the	O
discrete-time	O
Fourier	B-Algorithm
transform	I-Algorithm
(	O
DTFT	O
)	O
is	O
another	O
technique	O
which	O
is	O
often	O
used	O
in	O
system	O
analysis	O
.	O
</s>
<s>
With	O
a	O
1-D	O
DTFT	O
operation	O
,	O
GPGPU	B-Architecture
can	O
conceptually	O
reduce	O
the	O
complexity	O
from	O
Θ(n2 )	O
to	O
Θ(n )	O
as	O
illustrated	O
by	O
the	O
following	O
example	O
of	O
OpenCL	B-Application
implementation	O
.	O
</s>
<s>
That	O
is	O
,	O
an	O
M-D	O
DTFT	O
the	O
complexity	O
of	O
GPGPU	B-Architecture
can	O
be	O
computed	O
on	O
a	O
GPU	B-Architecture
with	O
a	O
complexity	O
of	O
Θ(n2 )	O
.	O
</s>
<s>
While	O
some	O
GPGPUs	B-Architecture
are	O
also	O
equipped	O
with	O
hardware	O
FFT	O
accelerators	O
internally	O
,	O
this	O
implementation	O
might	O
be	O
also	O
optimized	O
by	O
invoking	O
the	O
FFT	O
APIs	B-Application
or	O
libraries	O
provided	O
by	O
GPU	B-Architecture
manufacture	O
.	O
</s>
<s>
While	O
GPGPU	B-Architecture
computation	O
is	O
becoming	O
popular	O
,	O
several	O
adaptive	O
algorithms	O
have	O
been	O
proposed	O
to	O
design	O
multidimensional	O
FIR	O
and/or	O
IIR	O
filters	O
by	O
means	O
of	O
GPGPUs	B-Architecture
.	O
</s>
<s>
Traditionally	O
,	O
particularly	O
in	O
military	O
,	O
this	O
needs	O
supercomputers	B-Architecture
 '	O
support	O
.	O
</s>
<s>
Nowadays	O
,	O
GPGPUs	B-Architecture
are	O
also	O
employed	O
to	O
replace	O
supercomputers	B-Architecture
to	O
process	O
radar	O
signals	O
.	O
</s>
<s>
For	O
example	O
,	O
to	O
process	O
synthetic	B-Application
aperture	I-Application
radar	I-Application
(	O
SAR	O
)	O
signals	O
,	O
it	O
usually	O
involves	O
multidimensional	O
FFT	O
computations	O
.	O
</s>
<s>
GPGPUs	B-Architecture
can	O
be	O
used	O
to	O
rapidly	O
perform	O
FFT	O
and/or	O
iFFT	O
in	O
this	O
kind	O
of	O
applications	O
.	O
</s>
<s>
GPGPUs	B-Architecture
are	O
excellent	O
devices	O
to	O
achieve	O
the	O
goal	O
.	O
</s>
<s>
In	O
order	O
to	O
have	O
accurate	O
diagnosis	O
,	O
2-D	O
or	O
3-D	O
medical	O
signals	O
,	O
such	O
as	O
ultrasound	B-Application
,	O
X-ray	B-Library
,	O
MRI	O
,	O
and	O
CT	O
,	O
often	O
require	O
very	O
high	O
sampling	O
rate	O
and	O
image	O
resolutions	O
to	O
reconstruct	O
images	O
.	O
</s>
