<s>
A	O
multi-master	B-Architecture
bus	I-Architecture
is	O
a	O
computer	B-General_Concept
bus	I-General_Concept
in	O
which	O
there	O
are	O
multiple	O
bus	B-Architecture
master	I-Architecture
nodes	O
present	O
on	O
the	O
bus	O
.	O
</s>
<s>
For	O
example	O
,	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	O
)	O
is	O
used	O
to	O
transfer	O
data	O
between	O
peripherals	O
and	O
memory	O
without	O
the	O
need	O
to	O
use	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
.	O
</s>
