<s>
A	O
multi-core	B-Architecture
processor	I-Architecture
is	O
a	O
microprocessor	B-Architecture
on	O
a	O
single	O
integrated	O
circuit	O
with	O
two	O
or	O
more	O
separate	O
processing	B-General_Concept
units	I-General_Concept
,	O
called	O
cores	O
,	O
each	O
of	O
which	O
reads	O
and	O
executes	O
program	B-General_Concept
instructions	I-General_Concept
.	O
</s>
<s>
The	O
instructions	O
are	O
ordinary	O
CPU	B-General_Concept
instructions	I-General_Concept
(	O
such	O
as	O
add	O
,	O
move	O
data	O
,	O
and	O
branch	O
)	O
but	O
the	O
single	O
processor	O
can	O
run	O
instructions	O
on	O
separate	O
cores	O
at	O
the	O
same	O
time	O
,	O
increasing	O
overall	O
speed	O
for	O
programs	O
that	O
support	O
multithreading	B-Operating_System
or	O
other	O
parallel	B-Operating_System
computing	I-Operating_System
techniques	O
.	O
</s>
<s>
Manufacturers	O
typically	O
integrate	O
the	O
cores	O
onto	O
a	O
single	O
integrated	O
circuit	O
die	O
(	O
known	O
as	O
a	O
chip	B-Architecture
multiprocessor	I-Architecture
or	O
CMP	O
)	O
or	O
onto	O
multiple	O
dies	O
in	O
a	O
single	O
chip	B-Algorithm
package	I-Algorithm
.	O
</s>
<s>
The	O
microprocessors	B-Architecture
currently	O
used	O
in	O
almost	O
all	O
personal	O
computers	O
are	O
multi-core	B-Architecture
.	O
</s>
<s>
A	O
multi-core	B-Architecture
processor	I-Architecture
implements	O
multiprocessing	B-Operating_System
in	O
a	O
single	O
physical	O
package	O
.	O
</s>
<s>
Designers	O
may	O
couple	O
cores	O
in	O
a	O
multi-core	B-Architecture
device	O
tightly	O
or	O
loosely	O
.	O
</s>
<s>
For	O
example	O
,	O
cores	O
may	O
or	O
may	O
not	O
share	O
caches	B-General_Concept
,	O
and	O
they	O
may	O
implement	O
message	B-Architecture
passing	I-Architecture
or	O
shared-memory	B-Operating_System
inter-core	O
communication	O
methods	O
.	O
</s>
<s>
Common	O
network	B-Architecture
topologies	I-Architecture
used	O
to	O
interconnect	O
cores	O
include	O
bus	B-Architecture
,	O
ring	B-Architecture
,	O
two-dimensional	O
mesh	B-Architecture
,	O
and	O
crossbar	O
.	O
</s>
<s>
Homogeneous	O
multi-core	B-Architecture
systems	O
include	O
only	O
identical	O
cores	O
;	O
heterogeneous	O
multi-core	B-Architecture
systems	O
have	O
cores	O
that	O
are	O
not	O
identical	O
(	O
e.g.	O
</s>
<s>
big.LITTLE	B-Architecture
have	O
heterogeneous	O
cores	O
that	O
share	O
the	O
same	O
instruction	B-General_Concept
set	I-General_Concept
,	O
while	O
AMD	B-Architecture
Accelerated	I-Architecture
Processing	I-Architecture
Units	I-Architecture
have	O
cores	O
that	O
do	O
not	O
share	O
the	O
same	O
instruction	B-General_Concept
set	I-General_Concept
)	O
.	O
</s>
<s>
Just	O
as	O
with	O
single-processor	O
systems	O
,	O
cores	O
in	O
multi-core	B-Architecture
systems	O
may	O
implement	O
architectures	O
such	O
as	O
VLIW	B-General_Concept
,	O
superscalar	B-General_Concept
,	O
vector	B-Operating_System
,	O
or	O
multithreading	B-Operating_System
.	O
</s>
<s>
Multi-core	B-Architecture
processors	I-Architecture
are	O
widely	O
used	O
across	O
many	O
application	O
domains	O
,	O
including	O
general-purpose	O
,	O
embedded	B-Architecture
,	O
network	B-General_Concept
,	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
(	O
DSP	O
)	O
,	O
and	O
graphics	B-Architecture
(	O
GPU	B-Architecture
)	O
.	O
</s>
<s>
Core	O
count	O
goes	O
up	O
to	O
even	O
dozens	O
,	O
and	O
for	O
specialized	O
chips	O
over	O
10	O
,	O
000	O
,	O
and	O
in	O
supercomputers	B-Architecture
(	O
i.e.	O
</s>
<s>
The	O
improvement	O
in	O
performance	O
gained	O
by	O
the	O
use	O
of	O
a	O
multi-core	B-Architecture
processor	I-Architecture
depends	O
very	O
much	O
on	O
the	O
software	O
algorithms	O
used	O
and	O
their	O
implementation	O
.	O
</s>
<s>
In	O
particular	O
,	O
possible	O
gains	O
are	O
limited	O
by	O
the	O
fraction	O
of	O
the	O
software	O
that	O
can	O
run	B-Operating_System
in	I-Operating_System
parallel	I-Operating_System
simultaneously	O
on	O
multiple	O
cores	O
;	O
this	O
effect	O
is	O
described	O
by	O
Amdahl	B-Operating_System
's	I-Operating_System
law	I-Operating_System
.	O
</s>
<s>
In	O
the	O
best	O
case	O
,	O
so-called	O
embarrassingly	B-Operating_System
parallel	I-Operating_System
problems	I-Operating_System
may	O
realize	O
speedup	O
factors	O
near	O
the	O
number	O
of	O
cores	O
,	O
or	O
even	O
more	O
if	O
the	O
problem	O
is	O
split	O
up	O
enough	O
to	O
fit	O
within	O
each	O
core	O
's	O
cache(s )	O
,	O
avoiding	O
use	O
of	O
much	O
slower	O
main-system	O
memory	O
.	O
</s>
<s>
The	O
parallelization	B-Operating_System
of	O
software	O
is	O
a	O
significant	O
ongoing	O
topic	O
of	O
research	O
.	O
</s>
<s>
Cointegration	O
of	O
multiprocessor	B-Operating_System
applications	O
provides	O
flexibility	O
in	O
network	B-General_Concept
architecture	O
design	O
.	O
</s>
<s>
The	O
terms	O
multi-core	B-Architecture
and	O
dual-core	B-Architecture
most	O
commonly	O
refer	O
to	O
some	O
sort	O
of	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
,	O
but	O
are	O
sometimes	O
also	O
applied	O
to	O
digital	B-Architecture
signal	I-Architecture
processors	I-Architecture
(	O
DSP	O
)	O
and	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
(	O
SoC	O
)	O
.	O
</s>
<s>
The	O
terms	O
are	O
generally	O
used	O
only	O
to	O
refer	O
to	O
multi-core	B-Architecture
microprocessors	B-Architecture
that	O
are	O
manufactured	O
on	O
the	O
same	O
integrated	O
circuit	O
die	O
;	O
separate	O
microprocessor	B-Architecture
dies	O
in	O
the	O
same	O
package	O
are	O
generally	O
referred	O
to	O
by	O
another	O
name	O
,	O
such	O
as	O
multi-chip	B-Algorithm
module	I-Algorithm
.	O
</s>
<s>
This	O
article	O
uses	O
the	O
terms	O
"	O
multi-core	B-Architecture
"	O
and	O
"	O
dual-core	B-Architecture
"	O
for	O
CPUs	O
manufactured	O
on	O
the	O
same	O
integrated	O
circuit	O
,	O
unless	O
otherwise	O
noted	O
.	O
</s>
<s>
In	O
contrast	O
to	O
multi-core	B-Architecture
systems	O
,	O
the	O
term	O
multi-CPU	O
refers	O
to	O
multiple	O
physically	O
separate	O
processing-units	O
(	O
which	O
often	O
contain	O
special	O
circuitry	O
to	O
facilitate	O
communication	O
between	O
each	O
other	O
)	O
.	O
</s>
<s>
The	O
terms	O
many-core	B-General_Concept
and	O
massively	O
multi-core	B-Architecture
are	O
sometimes	O
used	O
to	O
describe	O
multi-core	B-Architecture
architectures	O
with	O
an	O
especially	O
high	O
number	O
of	O
cores	O
(	O
tens	O
to	O
thousands	O
)	O
.	O
</s>
<s>
Some	O
systems	O
use	O
many	O
soft	B-Device
microprocessor	I-Device
cores	O
placed	O
on	O
a	O
single	O
FPGA	B-Architecture
.	O
</s>
<s>
Each	O
"	O
core	O
"	O
can	O
be	O
considered	O
a	O
"	O
semiconductor	B-Architecture
intellectual	I-Architecture
property	I-Architecture
core	I-Architecture
"	O
as	O
well	O
as	O
a	O
CPU	B-Architecture
core	I-Architecture
.	O
</s>
<s>
Some	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
(	O
ILP	O
)	O
methods	O
such	O
as	O
superscalar	B-General_Concept
pipelining	B-General_Concept
are	O
suitable	O
for	O
many	O
applications	O
,	O
but	O
are	O
inefficient	O
for	O
others	O
that	O
contain	O
difficult-to-predict	O
code	O
.	O
</s>
<s>
Many	O
applications	O
are	O
better	O
suited	O
to	O
thread-level	B-Operating_System
parallelism	I-Operating_System
(	O
TLP	O
)	O
methods	O
,	O
and	O
multiple	O
independent	O
CPUs	O
are	O
commonly	O
used	O
to	O
increase	O
a	O
system	O
's	O
overall	O
TLP	O
.	O
</s>
<s>
A	O
combination	O
of	O
increased	O
available	O
space	O
(	O
due	O
to	O
refined	O
manufacturing	O
processes	O
)	O
and	O
the	O
demand	O
for	O
increased	O
TLP	O
led	O
to	O
the	O
development	O
of	O
multi-core	B-Architecture
CPUs	I-Architecture
.	O
</s>
<s>
Several	O
business	O
motives	O
drive	O
the	O
development	O
of	O
multi-core	B-Architecture
architectures	O
.	O
</s>
<s>
Alternatively	O
,	O
for	O
the	O
same	O
circuit	O
area	O
,	O
more	O
transistors	O
could	O
be	O
used	O
in	O
the	O
design	O
,	O
which	O
increased	O
functionality	O
,	O
especially	O
for	O
complex	B-Architecture
instruction	I-Architecture
set	I-Architecture
computing	I-Architecture
(	O
CISC	O
)	O
architectures	O
.	O
</s>
<s>
As	O
the	O
rate	O
of	O
clock	O
speed	O
improvements	O
slowed	O
,	O
increased	O
use	O
of	O
parallel	B-Operating_System
computing	I-Operating_System
in	O
the	O
form	O
of	O
multi-core	B-Architecture
processors	I-Architecture
has	O
been	O
pursued	O
to	O
improve	O
overall	O
processing	O
performance	O
.	O
</s>
<s>
Multiple	O
cores	O
were	O
used	O
on	O
the	O
same	O
CPU	B-Architecture
chip	I-Architecture
,	O
which	O
could	O
then	O
lead	O
to	O
better	O
sales	O
of	O
CPU	B-Architecture
chips	I-Architecture
with	O
two	O
or	O
more	O
cores	O
.	O
</s>
<s>
For	O
example	O
,	O
Intel	O
has	O
produced	O
a	O
48-core	O
processor	O
for	O
research	O
in	O
cloud	O
computing	O
;	O
each	O
core	O
has	O
an	O
x86	B-Operating_System
architecture	I-Operating_System
.	O
</s>
<s>
Since	O
computer	O
manufacturers	O
have	O
long	O
implemented	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
(	O
SMP	O
)	O
designs	O
using	O
discrete	O
CPUs	O
,	O
the	O
issues	O
regarding	O
implementing	O
multi-core	B-Architecture
processor	I-Architecture
architecture	O
and	O
supporting	O
it	O
with	O
software	O
are	O
well	O
known	O
.	O
</s>
<s>
For	O
general-purpose	O
processors	O
,	O
much	O
of	O
the	O
motivation	O
for	O
multi-core	B-Architecture
processors	I-Architecture
comes	O
from	O
greatly	O
diminished	O
gains	O
in	O
processor	O
performance	O
from	O
increasing	O
the	O
operating	B-General_Concept
frequency	I-General_Concept
.	O
</s>
<s>
The	O
ILP	O
wall	O
;	O
the	O
increasing	O
difficulty	O
of	O
finding	O
enough	O
parallelism	B-Operating_System
in	I-Operating_System
a	I-Operating_System
single	I-Operating_System
instruction	I-Operating_System
stream	I-Operating_System
to	O
keep	O
a	O
high-performance	O
single-core	O
processor	O
busy	O
.	O
</s>
<s>
The	O
power	O
wall	O
;	O
the	O
trend	O
of	O
consuming	O
exponentially	O
increasing	O
power	O
(	O
and	O
thus	O
also	O
generating	O
exponentially	O
increasing	O
heat	O
)	O
with	O
each	O
factorial	O
increase	O
of	O
operating	B-General_Concept
frequency	I-General_Concept
.	O
</s>
<s>
In	O
order	O
to	O
continue	O
delivering	O
regular	O
performance	O
improvements	O
for	O
general-purpose	O
processors	O
,	O
manufacturers	O
such	O
as	O
Intel	O
and	O
AMD	O
have	O
turned	O
to	O
multi-core	B-Architecture
designs	O
,	O
sacrificing	O
lower	O
manufacturing-costs	O
for	O
higher	O
performance	O
in	O
some	O
applications	O
and	O
systems	O
.	O
</s>
<s>
Multi-core	B-Architecture
architectures	O
are	O
being	O
developed	O
,	O
but	O
so	O
are	O
the	O
alternatives	O
.	O
</s>
<s>
The	O
proximity	O
of	O
multiple	O
CPU	B-Architecture
cores	I-Architecture
on	O
the	O
same	O
die	O
allows	O
the	O
cache	B-General_Concept
coherency	I-General_Concept
circuitry	O
to	O
operate	O
at	O
a	O
much	O
higher	O
clock	O
rate	O
than	O
what	O
is	O
possible	O
if	O
the	O
signals	O
have	O
to	O
travel	O
off-chip	O
.	O
</s>
<s>
Combining	O
equivalent	O
CPUs	O
on	O
a	O
single	O
die	O
significantly	O
improves	O
the	O
performance	O
of	O
cache	B-General_Concept
snoop	I-General_Concept
(	O
alternative	O
:	O
Bus	B-General_Concept
snooping	I-General_Concept
)	O
operations	O
.	O
</s>
<s>
Assuming	O
that	O
the	O
die	O
can	O
physically	O
fit	O
into	O
the	O
package	O
,	O
multi-core	B-Architecture
CPU	I-Architecture
designs	O
require	O
much	O
less	O
printed	O
circuit	O
board	O
(	O
PCB	O
)	O
space	O
than	O
do	O
multi-chip	O
SMP	O
designs	O
.	O
</s>
<s>
Also	O
,	O
a	O
dual-core	B-Architecture
processor	I-Architecture
uses	O
slightly	O
less	O
power	O
than	O
two	O
coupled	O
single-core	O
processors	O
,	O
principally	O
because	O
of	O
the	O
decreased	O
power	O
required	O
to	O
drive	O
signals	O
external	O
to	O
the	O
chip	O
.	O
</s>
<s>
Furthermore	O
,	O
the	O
cores	O
share	O
some	O
circuitry	O
,	O
like	O
the	O
L2	O
cache	O
and	O
the	O
interface	O
to	O
the	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	O
)	O
.	O
</s>
<s>
In	O
terms	O
of	O
competing	O
technologies	O
for	O
the	O
available	O
silicon	O
die	O
area	O
,	O
multi-core	B-Architecture
design	O
can	O
make	O
use	O
of	O
proven	O
CPU	B-Architecture
core	I-Architecture
library	O
designs	O
and	O
produce	O
a	O
product	O
with	O
lower	O
risk	O
of	O
design	O
error	O
than	O
devising	O
a	O
new	O
wider-core	O
design	O
.	O
</s>
<s>
Multi-core	B-Architecture
chips	O
also	O
allow	O
higher	O
performance	O
at	O
lower	O
energy	O
.	O
</s>
<s>
Since	O
each	O
core	O
in	O
a	O
multi-core	B-Architecture
CPU	I-Architecture
is	O
generally	O
more	O
energy-efficient	O
,	O
the	O
chip	O
becomes	O
more	O
efficient	O
than	O
having	O
a	O
single	O
large	O
monolithic	O
core	O
.	O
</s>
<s>
A	O
challenge	O
in	O
this	O
,	O
however	O
,	O
is	O
the	O
additional	O
overhead	O
of	O
writing	O
parallel	B-Operating_System
code	I-Operating_System
.	O
</s>
<s>
Maximizing	O
the	O
usage	O
of	O
the	O
computing	O
resources	O
provided	O
by	O
multi-core	B-Architecture
processors	I-Architecture
requires	O
adjustments	O
both	O
to	O
the	O
operating	B-General_Concept
system	I-General_Concept
(	O
OS	O
)	O
support	O
and	O
to	O
existing	O
application	O
software	O
.	O
</s>
<s>
Also	O
,	O
the	O
ability	O
of	O
multi-core	B-Architecture
processors	I-Architecture
to	O
increase	O
application	O
performance	O
depends	O
on	O
the	O
use	O
of	O
multiple	O
threads	B-Operating_System
within	O
applications	O
.	O
</s>
<s>
Integration	O
of	O
a	O
multi-core	B-Architecture
chip	O
can	O
lower	O
the	O
chip	O
production	O
yields	O
.	O
</s>
<s>
Intel	O
has	O
partially	O
countered	O
this	O
first	O
problem	O
by	O
creating	O
its	O
quad-core	B-Architecture
designs	O
by	O
combining	O
two	O
dual-core	B-Architecture
ones	O
on	O
a	O
single	O
die	O
with	O
a	O
unified	O
cache	O
,	O
hence	O
any	O
two	O
working	O
dual-core	B-Architecture
dies	O
can	O
be	O
used	O
,	O
as	O
opposed	O
to	O
producing	O
four	O
cores	O
on	O
a	O
single	O
die	O
and	O
requiring	O
all	O
four	O
to	O
work	O
to	O
produce	O
a	O
quad-core	B-Architecture
CPU	O
.	O
</s>
<s>
From	O
an	O
architectural	O
point	O
of	O
view	O
,	O
ultimately	O
,	O
single	O
CPU	O
designs	O
may	O
make	O
better	O
use	O
of	O
the	O
silicon	O
surface	O
area	O
than	O
multiprocessing	B-Operating_System
cores	O
,	O
so	O
a	O
development	O
commitment	O
to	O
this	O
architecture	O
may	O
carry	O
the	O
risk	O
of	O
obsolescence	O
.	O
</s>
<s>
Two	O
processing	O
cores	O
sharing	O
the	O
same	O
system	O
bus	B-Architecture
and	O
memory	O
bandwidth	O
limits	O
the	O
real-world	O
performance	O
advantage	O
.	O
</s>
<s>
In	O
a	O
2009	O
report	O
,	O
Dr	O
Jun	O
Ni	O
showed	O
that	O
if	O
a	O
single	O
core	O
is	O
close	O
to	O
being	O
memory-bandwidth	O
limited	O
,	O
then	O
going	O
to	O
dual-core	B-Architecture
might	O
give	O
30%	O
to	O
70%	O
improvement	O
;	O
if	O
memory	O
bandwidth	O
is	O
not	O
a	O
problem	O
,	O
then	O
a	O
90%	O
improvement	O
can	O
be	O
expected	O
;	O
however	O
,	O
Amdahl	B-Operating_System
's	I-Operating_System
law	I-Operating_System
makes	O
this	O
claim	O
dubious	O
.	O
</s>
<s>
In	O
addition	O
,	O
multi-core	B-Architecture
chips	O
mixed	O
with	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
,	O
memory-on-chip	O
,	O
and	O
special-purpose	O
"	O
heterogeneous	O
"	O
(	O
or	O
asymmetric	O
)	O
cores	O
promise	O
further	O
performance	O
and	O
efficiency	O
gains	O
,	O
especially	O
in	O
processing	O
multimedia	O
,	O
recognition	O
and	O
networking	O
applications	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
big.LITTLE	B-Architecture
core	O
includes	O
a	O
high-performance	O
core	O
(	O
called	O
'	O
big	O
 '	O
)	O
and	O
a	O
low-power	O
core	O
(	O
called	O
'	O
LITTLE	O
 '	O
)	O
.	O
</s>
<s>
There	O
is	O
also	O
a	O
trend	O
towards	O
improving	O
energy-efficiency	O
by	O
focusing	O
on	O
performance-per-watt	O
with	O
advanced	O
fine-grain	O
or	O
ultra	O
fine-grain	O
power	O
management	O
and	O
dynamic	B-General_Concept
voltage	I-General_Concept
and	I-General_Concept
frequency	I-General_Concept
scaling	I-General_Concept
(	O
i.e.	O
</s>
<s>
laptop	B-Device
computers	I-Device
and	O
portable	O
media	O
players	O
)	O
.	O
</s>
<s>
Chips	O
designed	O
from	O
the	O
outset	O
for	O
a	O
large	O
number	O
of	O
cores	O
(	O
rather	O
than	O
having	O
evolved	O
from	O
single	O
core	O
designs	O
)	O
are	O
sometimes	O
referred	O
to	O
as	O
manycore	B-General_Concept
designs	O
,	O
emphasising	O
qualitative	O
differences	O
.	O
</s>
<s>
The	O
composition	O
and	O
balance	O
of	O
the	O
cores	O
in	O
multi-core	B-Architecture
architecture	O
show	O
great	O
variety	O
.	O
</s>
<s>
A	O
device	O
advertised	O
as	O
being	O
octa-core	B-Architecture
will	O
only	O
have	O
independent	O
cores	O
if	O
advertised	O
as	O
True	O
Octa-core	B-Architecture
,	O
or	O
similar	O
styling	O
,	O
as	O
opposed	O
to	O
being	O
merely	O
two	O
sets	O
of	O
quad-cores	B-Architecture
each	O
with	O
fixed	O
clock	O
speeds	O
.	O
</s>
<s>
The	O
article	O
"	O
CPU	O
designers	O
debate	O
multi-core	B-Architecture
future	O
"	O
by	O
Rick	O
Merritt	O
,	O
EE	O
Times	O
2008	O
,	O
includes	O
these	O
comments	O
:	O
</s>
<s>
An	O
outdated	O
version	O
of	O
an	O
anti-virus	O
application	O
may	O
create	O
a	O
new	O
thread	B-Operating_System
for	O
a	O
scan	O
process	O
,	O
while	O
its	O
GUI	B-Application
thread	B-Operating_System
waits	O
for	O
commands	O
from	O
the	O
user	O
(	O
e.g.	O
</s>
<s>
In	O
such	O
cases	O
,	O
a	O
multi-core	B-Architecture
architecture	O
is	O
of	O
little	O
benefit	O
for	O
the	O
application	O
itself	O
due	O
to	O
the	O
single	B-Operating_System
thread	I-Operating_System
doing	O
all	O
the	O
heavy	O
lifting	O
and	O
the	O
inability	O
to	O
balance	O
the	O
work	O
evenly	O
across	O
multiple	O
cores	O
.	O
</s>
<s>
Programming	O
truly	O
multithreaded	O
code	O
often	O
requires	O
complex	O
co-ordination	O
of	O
threads	B-Operating_System
and	O
can	O
easily	O
introduce	O
subtle	O
and	O
difficult-to-find	O
bugs	O
due	O
to	O
the	O
interweaving	O
of	O
processing	O
on	O
data	O
shared	O
between	O
threads	B-Operating_System
(	O
see	O
thread-safety	B-Operating_System
)	O
.	O
</s>
<s>
Consequently	O
,	O
such	O
code	O
is	O
much	O
more	O
difficult	O
to	O
debug	O
than	O
single-threaded	B-Operating_System
code	O
when	O
it	O
breaks	O
.	O
</s>
<s>
Also	O
,	O
serial	O
tasks	O
like	O
decoding	O
the	O
entropy	B-Algorithm
encoding	I-Algorithm
algorithms	O
used	O
in	O
video	B-Application
codecs	I-Application
are	O
impossible	O
to	O
parallelize	O
because	O
each	O
result	O
generated	O
is	O
used	O
to	O
help	O
create	O
the	O
next	O
result	O
of	O
the	O
entropy	O
decoding	O
algorithm	O
.	O
</s>
<s>
Given	O
the	O
increasing	O
emphasis	O
on	O
multi-core	B-Architecture
chip	O
design	O
,	O
stemming	O
from	O
the	O
grave	O
thermal	O
and	O
power	O
consumption	O
problems	O
posed	O
by	O
any	O
further	O
significant	O
increase	O
in	O
processor	O
clock	O
speeds	O
,	O
the	O
extent	O
to	O
which	O
software	O
can	O
be	O
multithreaded	O
to	O
take	O
advantage	O
of	O
these	O
new	O
chips	O
is	O
likely	O
to	O
be	O
the	O
single	O
greatest	O
constraint	O
on	O
computer	O
performance	O
in	O
the	O
future	O
.	O
</s>
<s>
The	O
telecommunications	O
market	O
had	O
been	O
one	O
of	O
the	O
first	O
that	O
needed	O
a	O
new	O
design	O
of	O
parallel	O
datapath	O
packet	O
processing	O
because	O
there	O
was	O
a	O
very	O
quick	O
adoption	O
of	O
these	O
multiple-core	B-Architecture
processors	I-Architecture
for	O
the	O
datapath	O
and	O
the	O
control	O
plane	O
.	O
</s>
<s>
These	O
MPUs	O
are	O
going	O
to	O
replace	O
the	O
traditional	O
Network	B-General_Concept
Processors	I-General_Concept
that	O
were	O
based	O
on	O
proprietary	O
microcode	B-Device
or	O
picocode	B-Device
.	O
</s>
<s>
Parallel	B-Operating_System
programming	I-Operating_System
techniques	O
can	O
benefit	O
from	O
multiple	O
cores	O
directly	O
.	O
</s>
<s>
Some	O
existing	O
parallel	B-Application
programming	I-Application
models	I-Application
such	O
as	O
Cilk	O
Plus	O
,	O
OpenMP	B-Application
,	O
OpenHMPP	B-Application
,	O
FastFlow	O
,	O
Skandium	O
,	O
MPI	B-Application
,	O
and	O
Erlang	B-Operating_System
can	O
be	O
used	O
on	O
multi-core	B-Architecture
platforms	O
.	O
</s>
<s>
Intel	O
introduced	O
a	O
new	O
abstraction	O
for	O
C++	O
parallelism	B-Operating_System
called	O
TBB	B-Application
.	O
</s>
<s>
Other	O
research	O
efforts	O
include	O
the	O
Codeplay	B-Language
Sieve	I-Language
System	I-Language
,	O
Cray	O
's	O
Chapel	B-Language
,	O
Sun	O
's	O
Fortress	B-Language
,	O
and	O
IBM	O
's	O
X10	B-Language
.	O
</s>
<s>
Multi-core	B-Architecture
processing	O
has	O
also	O
affected	O
the	O
ability	O
of	O
modern	O
computational	O
software	O
development	O
.	O
</s>
<s>
Developers	O
programming	O
in	O
newer	O
languages	O
might	O
find	O
that	O
their	O
modern	O
languages	O
do	O
not	O
support	O
multi-core	B-Architecture
functionality	O
.	O
</s>
<s>
This	O
then	O
requires	O
the	O
use	O
of	O
numerical	B-Library
libraries	I-Library
to	O
access	O
code	O
written	O
in	O
languages	O
like	O
C	B-Language
and	O
Fortran	B-Application
,	O
which	O
perform	O
math	O
computations	O
faster	O
than	O
newer	O
languages	O
like	O
C#	B-Application
.	O
</s>
<s>
Intel	O
's	O
MKL	O
and	O
AMD	O
's	O
ACML	B-Library
are	O
written	O
in	O
these	O
native	O
languages	O
and	O
take	O
advantage	O
of	O
multi-core	B-Architecture
processing	O
.	O
</s>
<s>
Managing	O
concurrency	B-Architecture
acquires	O
a	O
central	O
role	O
in	O
developing	O
parallel	O
applications	O
.	O
</s>
<s>
Developers	O
revisit	O
decisions	O
made	O
in	O
the	O
partitioning	O
and	O
communication	O
phases	O
with	O
a	O
view	O
to	O
obtaining	O
an	O
algorithm	O
that	O
will	O
execute	O
efficiently	O
on	O
some	O
class	O
of	O
parallel	B-Operating_System
computer	I-Operating_System
.	O
</s>
<s>
This	O
mapping	O
problem	O
does	O
not	O
arise	O
on	O
uniprocessors	O
or	O
on	O
shared-memory	B-Operating_System
computers	O
that	O
provide	O
automatic	O
task	O
scheduling	O
.	O
</s>
<s>
On	O
the	O
other	O
hand	O
,	O
on	O
the	O
server	B-Application
side	I-Application
,	O
multi-core	B-Architecture
processors	I-Architecture
are	O
ideal	O
because	O
they	O
allow	O
many	O
users	O
to	O
connect	O
to	O
a	O
site	O
simultaneously	O
and	O
have	O
independent	O
threads	B-Operating_System
of	O
execution	O
.	O
</s>
<s>
Initially	O
,	O
for	O
some	O
of	O
its	O
enterprise	O
software	O
,	O
Microsoft	O
continued	O
to	O
use	O
a	O
per-socket	O
licensing	O
system	O
.	O
</s>
<s>
However	O
,	O
for	O
some	O
software	O
such	O
as	O
BizTalk	B-Application
Server	I-Application
2013	I-Application
,	O
SQL	B-Application
Server	I-Application
2014	I-Application
,	O
and	O
Windows	B-Device
Server	I-Device
2016	I-Device
,	O
Microsoft	O
has	O
shifted	O
to	O
per-core	O
licensing	O
.	O
</s>
<s>
Oracle	B-Application
Corporation	I-Application
counts	O
an	O
AMD	O
X2	O
or	O
an	O
Intel	O
dual-core	B-Architecture
CPU	O
as	O
a	O
single	O
processor	O
but	O
uses	O
other	O
metrics	O
for	O
other	O
types	O
,	O
especially	O
for	O
processors	O
with	O
more	O
than	O
two	O
cores	O
.	O
</s>
<s>
Embedded	B-Architecture
computing	I-Architecture
operates	O
in	O
an	O
area	O
of	O
processor	O
technology	O
distinct	O
from	O
that	O
of	O
"	O
mainstream	O
"	O
PCs	O
.	O
</s>
<s>
The	O
same	O
technological	O
drives	O
towards	O
multi-core	B-Architecture
apply	O
here	O
too	O
.	O
</s>
<s>
Indeed	O
,	O
in	O
many	O
cases	O
the	O
application	O
is	O
a	O
"	O
natural	O
"	O
fit	O
for	O
multi-core	B-Architecture
technologies	O
,	O
if	O
the	O
task	O
can	O
easily	O
be	O
partitioned	O
between	O
the	O
different	O
processors	O
.	O
</s>
<s>
In	O
addition	O
,	O
embedded	B-Architecture
software	O
is	O
typically	O
developed	O
for	O
a	O
specific	O
hardware	O
release	O
,	O
making	O
issues	O
of	O
software	B-Architecture
portability	I-Architecture
,	O
legacy	O
code	O
or	O
supporting	O
independent	O
developers	O
less	O
critical	O
than	O
is	O
the	O
case	O
for	O
PC	O
or	O
enterprise	O
computing	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
it	O
is	O
easier	O
for	O
developers	O
to	O
adopt	O
new	O
technologies	O
and	O
as	O
a	O
result	O
there	O
is	O
a	O
greater	O
variety	O
of	O
multi-core	B-Architecture
processing	O
architectures	O
and	O
suppliers	O
.	O
</s>
<s>
,	O
multi-core	B-Architecture
network	B-General_Concept
processors	I-General_Concept
have	O
become	O
mainstream	O
,	O
with	O
companies	O
such	O
as	O
Freescale	O
Semiconductor	O
,	O
Cavium	O
Networks	O
,	O
Wintegra	O
and	O
Broadcom	O
all	O
manufacturing	O
products	O
with	O
eight	O
processors	O
.	O
</s>
<s>
For	O
the	O
system	O
developer	O
,	O
a	O
key	O
challenge	O
is	O
how	O
to	O
exploit	O
all	O
the	O
cores	O
in	O
these	O
devices	O
to	O
achieve	O
maximum	O
networking	O
performance	O
at	O
the	O
system	O
level	O
,	O
despite	O
the	O
performance	O
limitations	O
inherent	O
in	O
a	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
(	O
SMP	O
)	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
Companies	O
such	O
as	O
6WIND	O
provide	O
portable	O
packet	O
processing	O
software	O
designed	O
so	O
that	O
the	O
networking	O
data	O
plane	O
runs	O
in	O
a	O
fast	O
path	O
environment	O
outside	O
the	O
operating	B-General_Concept
system	I-General_Concept
of	O
the	O
network	B-General_Concept
device	O
.	O
</s>
<s>
In	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
the	O
same	O
trend	O
applies	O
:	O
Texas	O
Instruments	O
has	O
the	O
three-core	O
TMS320C6488	O
and	O
four-core	O
TMS320C5441	O
,	O
Freescale	O
the	O
four-core	O
MSC8144	O
and	O
six-core	O
MSC8156	O
(	O
and	O
both	O
have	O
stated	O
they	O
are	O
working	O
on	O
eight-core	O
successors	O
)	O
.	O
</s>
<s>
Newer	O
entries	O
include	O
the	O
Storm-1	O
family	O
from	O
with	O
40	O
and	O
80	O
general	O
purpose	O
ALUs	O
per	O
chip	O
,	O
all	O
programmable	O
in	O
C	B-Language
as	O
a	O
SIMD	O
engine	O
and	O
Picochip	B-General_Concept
with	O
300	O
processors	O
on	O
a	O
single	O
die	O
,	O
focused	O
on	O
communication	O
applications	O
.	O
</s>
<s>
In	O
heterogeneous	O
computing	O
,	O
where	O
a	O
system	O
uses	O
more	O
than	O
one	O
kind	O
of	O
processor	O
or	O
cores	O
,	O
multi-core	B-Architecture
solutions	O
are	O
becoming	O
more	O
common	O
:	O
Xilinx	O
Zynq	O
UltraScale+	O
MPSoC	O
has	O
a	O
quad-core	B-Architecture
ARM	B-Architecture
Cortex-A53	O
and	O
dual-core	B-Architecture
ARM	B-Architecture
Cortex-R5	O
.	O
</s>
<s>
Mobile	O
devices	O
may	O
use	O
the	O
ARM	B-Architecture
big.LITTLE	I-Architecture
architecture	O
.	O
</s>
<s>
Adapteva	B-Application
Epiphany	I-Application
,	O
a	O
many-core	B-General_Concept
processor	I-General_Concept
architecture	O
which	O
allows	O
up	O
to	O
4096	O
processors	O
on-chip	O
,	O
although	O
only	O
a	O
16-core	O
version	O
has	O
been	O
commercially	O
produced	O
.	O
</s>
<s>
Aeroflex	O
Gaisler	O
LEON3	O
,	O
a	O
multi-core	B-Architecture
SPARC	B-Architecture
that	O
also	O
exists	O
in	O
a	O
fault-tolerant	O
version	O
.	O
</s>
<s>
Ageia	B-Operating_System
PhysX	I-Operating_System
,	O
a	O
multi-core	B-Architecture
physics	O
processing	O
unit	O
.	O
</s>
<s>
A-Series	B-Architecture
,	O
dual-	O
,	O
triple-	O
,	O
and	O
quad-core	B-Architecture
of	O
Accelerated	O
Processor	O
Units	O
(	O
APU	O
)	O
.	O
</s>
<s>
Athlon	O
64	O
FX	O
and	O
Athlon	O
64	O
X2	O
single	O
-	O
and	O
dual-core	B-Architecture
desktop	O
processors	O
.	O
</s>
<s>
Athlon	O
II	O
,	O
dual-	O
,	O
triple-	O
,	O
and	O
quad-core	B-Architecture
desktop	O
processors	O
.	O
</s>
<s>
Opteron	B-General_Concept
,	O
single-	O
,	O
dual-	O
,	O
quad-	O
,	O
6-	O
,	O
8-	O
,	O
12-	O
,	O
and	O
16-core	O
server/workstation	O
processors	O
.	O
</s>
<s>
Phenom	O
,	O
dual-	O
,	O
triple-	O
,	O
and	O
quad-core	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
Sempron	O
,	O
single-	O
,	O
dual-	O
,	O
and	O
quad-core	B-Architecture
entry	O
level	O
processors	O
.	O
</s>
<s>
Turion	O
,	O
single	O
-	O
and	O
dual-core	B-Architecture
laptop	B-Device
processors	O
.	O
</s>
<s>
Ryzen	O
,	O
dual-	O
,	O
quad-	O
,	O
6-	O
,	O
8-	O
,	O
12-	O
,	O
16-	O
,	O
24-	O
,	O
32-	O
,	O
and	O
64-core	O
desktop	O
,	O
mobile	O
,	O
and	O
embedded	B-Architecture
platform	O
processors	O
.	O
</s>
<s>
Epyc	O
,	O
quad-	O
,	O
8-	O
,	O
12-	O
,	O
16-	O
,	O
24-	O
,	O
32-	O
,	O
and	O
64-core	O
server	O
and	O
embedded	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
Radeon	B-Device
and	O
FireStream	O
GPU/GPGPU	O
.	O
</s>
<s>
ARM	B-Architecture
MPCore	O
is	O
a	O
fully	O
synthesizable	O
multi-core	B-Architecture
container	O
for	O
ARM11	O
MPCore	O
and	O
ARM	B-Application
Cortex-A9	I-Application
MPCore	I-Application
processor	O
cores	O
,	O
intended	O
for	O
high-performance	O
embedded	B-Architecture
and	O
entertainment	O
applications	O
.	O
</s>
<s>
ASOCS	B-Application
ModemX	O
,	O
up	O
to	O
128	O
cores	O
,	O
wireless	O
applications	O
.	O
</s>
<s>
Cradle	O
Technologies	O
CT3400	O
and	O
CT3600	O
,	O
both	O
multi-core	B-Architecture
DSPs	O
.	O
</s>
<s>
Cavium	O
Networks	O
Octeon	O
,	O
a	O
32-core	O
MIPS	B-Device
MPU	B-Architecture
.	O
</s>
<s>
Freescale	O
Semiconductor	O
QorIQ	O
series	O
processors	O
,	O
up	O
to	O
8	O
cores	O
,	O
Power	B-Architecture
ISA	I-Architecture
MPU	B-Architecture
.	O
</s>
<s>
Hewlett-Packard	O
PA-8800	B-General_Concept
and	O
PA-8900	B-General_Concept
,	O
dual	B-Architecture
core	I-Architecture
PA-RISC	B-Device
processors	O
.	O
</s>
<s>
POWER4	B-Device
,	O
a	O
dual-core	B-Architecture
PowerPC	B-Architecture
processor	I-Architecture
,	O
released	O
in	O
2001	O
.	O
</s>
<s>
POWER5	B-Device
,	O
a	O
dual-core	B-Architecture
PowerPC	B-Architecture
processor	I-Architecture
,	O
released	O
in	O
2004	O
.	O
</s>
<s>
POWER6	B-Device
,	O
a	O
dual-core	B-Architecture
PowerPC	B-Architecture
processor	I-Architecture
,	O
released	O
in	O
2007	O
.	O
</s>
<s>
POWER7	B-Device
,	O
a	O
4	O
,	O
6	O
,	O
8-core	O
PowerPC	B-Architecture
processor	I-Architecture
,	O
released	O
in	O
2010	O
.	O
</s>
<s>
POWER8	B-Device
,	O
a	O
12-core	O
PowerPC	B-Architecture
processor	I-Architecture
,	O
released	O
in	O
2013	O
.	O
</s>
<s>
POWER9	B-Device
,	O
a	O
12	O
or	O
24-core	O
PowerPC	B-Architecture
processor	I-Architecture
,	O
released	O
in	O
2017	O
.	O
</s>
<s>
Power10	B-Operating_System
,	O
a	O
15	O
or	O
30-core	O
PowerPC	B-Architecture
processor	I-Architecture
,	O
released	O
in	O
2021	O
.	O
</s>
<s>
PowerPC	B-Architecture
970MP	B-General_Concept
,	O
a	O
dual-core	B-Architecture
PowerPC	B-Architecture
processor	I-Architecture
,	O
used	O
in	O
the	O
Apple	O
Power	B-Device
Mac	I-Device
G5	I-Device
.	O
</s>
<s>
Xenon	B-Operating_System
,	O
a	O
triple-core	B-Architecture
,	O
SMT-capable	O
,	O
PowerPC	B-Architecture
microprocessor	B-Architecture
used	O
in	O
the	O
Microsoft	B-Operating_System
Xbox	I-Operating_System
360	I-Operating_System
game	O
console	O
.	O
</s>
<s>
z10	B-Device
,	O
a	O
quad-core	B-Architecture
z/Architecture	B-Device
processor	O
,	O
released	O
in	O
2008	O
.	O
</s>
<s>
z196	B-Device
,	O
a	O
quad-core	B-Architecture
z/Architecture	B-Device
processor	O
,	O
released	O
in	O
2010	O
.	O
</s>
<s>
zEC12	B-Device
,	O
a	O
six-core	O
z/Architecture	B-Device
processor	O
,	O
released	O
in	O
2012	O
.	O
</s>
<s>
z13	B-Device
,	O
an	O
eight-core	O
z/Architecture	B-Device
processor	O
,	O
released	O
in	O
2015	O
.	O
</s>
<s>
z14	B-Device
,	O
a	O
ten-core	O
z/Architecture	B-Device
processor	O
,	O
released	O
in	O
2017	O
.	O
</s>
<s>
z15	B-Device
,	O
a	O
twelve-core	O
z/Architecture	B-Device
processor	O
,	O
released	O
in	O
2019	O
.	O
</s>
<s>
Telum	B-Device
,	O
an	O
eight-core	O
z/Architecture	B-Device
processor	O
,	O
released	O
in	O
2021	O
.	O
</s>
<s>
Danube	O
,	O
a	O
dual-core	B-Architecture
,	O
MIPS-based	O
,	O
home	B-Application
gateway	I-Application
processor	O
.	O
</s>
<s>
Atom	B-Application
,	O
single	O
,	O
dual-core	B-Architecture
,	O
quad-core	B-Architecture
,	O
8-	O
,	O
12-	O
,	O
and	O
16-core	O
processors	O
for	O
netbooks	B-Device
,	O
nettops	B-Protocol
,	O
embedded	B-Architecture
applications	O
,	O
and	O
mobile	B-Device
internet	I-Device
devices	I-Device
(	O
MIDs	O
)	O
.	O
</s>
<s>
Atom	B-Application
SoC	I-Application
(	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
)	O
,	O
single-core	O
,	O
dual-core	B-Architecture
,	O
and	O
quad-core	B-Architecture
processors	I-Architecture
for	O
smartphones	O
and	O
tablets	O
.	O
</s>
<s>
Celeron	B-Device
,	O
the	O
first	O
dual-core	B-Architecture
(	O
and	O
,	O
later	O
,	O
quad-core	B-Architecture
)	O
processor	O
for	O
the	O
budget/entry	O
-level	O
market	O
.	O
</s>
<s>
Core	O
Duo	O
,	O
a	O
dual-core	B-Architecture
processor	I-Architecture
.	O
</s>
<s>
Core	O
2	O
Duo	O
,	O
a	O
dual-core	B-Architecture
processor	I-Architecture
.	O
</s>
<s>
Core	O
2	O
Quad	O
,	O
2	O
dual-core	B-Architecture
dies	O
packaged	O
in	O
a	O
multi-chip	B-Algorithm
module	I-Algorithm
.	O
</s>
<s>
Core	B-Device
i3	I-Device
,	O
Core	B-Device
i5	I-Device
,	O
Core	B-Device
i7	I-Device
and	O
Core	B-Device
i9	I-Device
,	O
a	O
family	O
of	O
dual-	O
,	O
quad-	O
,	O
6-	O
,	O
8-	O
,	O
10-	O
,	O
12-	O
,	O
14-	O
,	O
16-	O
,	O
and	O
18-core	O
processors	O
,	O
and	O
the	O
successor	O
of	O
the	O
Core	O
2	O
Duo	O
and	O
the	O
Core	O
2	O
Quad	O
.	O
</s>
<s>
Itanium	B-General_Concept
,	O
single	O
,	O
dual-core	B-Architecture
,	O
quad-core	B-Architecture
,	O
and	O
8-core	O
processors	O
.	O
</s>
<s>
Pentium	B-General_Concept
,	O
single	O
,	O
dual-core	B-Architecture
,	O
and	O
quad-core	B-Architecture
processors	I-Architecture
for	O
the	O
entry-level	O
market	O
.	O
</s>
<s>
Teraflops	B-General_Concept
Research	I-General_Concept
Chip	I-General_Concept
(	O
Polaris	B-General_Concept
)	O
,	O
a	O
3.16GHz	O
,	O
80-core	O
processor	O
prototype	O
,	O
which	O
the	O
company	O
originally	O
stated	O
would	O
be	O
released	O
by	O
2011	O
.	O
</s>
<s>
Xeon	B-Device
dual-	O
,	O
quad-	O
,	O
6-	O
,	O
8-	O
,	O
10-	O
,	O
12-	O
,	O
14-	O
,	O
15-	O
,	O
16-	O
,	O
18-	O
,	O
20-	O
,	O
22-	O
,	O
24-	O
,	O
26-	O
,	O
28-	O
,	O
32-	O
,	O
48-	O
,	O
and	O
56-core	O
processors	O
.	O
</s>
<s>
Xeon	B-Device
Phi	O
57-	O
,	O
60-	O
,	O
61-	O
,	O
64-	O
,	O
68-	O
,	O
and	O
72-core	O
processors	O
.	O
</s>
<s>
RTX	B-Device
3090	I-Device
(	O
10496	O
CUDA	B-Architecture
cores	O
,	O
GPGPU	B-Architecture
cores	O
;	O
plus	O
other	O
more	O
specialized	O
cores	O
)	O
.	O
</s>
<s>
Parallax	B-Architecture
Propeller	I-Architecture
P8X32	B-Architecture
,	O
an	O
eight-core	O
microcontroller	O
.	O
</s>
<s>
picoChip	B-General_Concept
PC200	O
series	O
200	O
–	O
300	O
cores	O
per	O
device	O
for	O
DSP	O
&	O
wireless	O
.	O
</s>
<s>
Plurality	O
HAL	O
series	O
tightly	O
coupled	O
16-256	O
cores	O
,	O
L1	O
shared	B-Operating_System
memory	I-Operating_System
,	O
hardware	O
synchronized	O
processor	O
.	O
</s>
<s>
Rapport	O
Kilocore	B-General_Concept
KC256	O
,	O
a	O
257-core	O
microcontroller	O
with	O
a	O
PowerPC	B-Architecture
core	O
and	O
256	O
8-bit	O
"	O
processing	O
elements	O
"	O
.	O
</s>
<s>
SiCortex	B-Operating_System
"	O
SiCortex	B-Operating_System
node	O
"	O
has	O
six	O
MIPS64	O
cores	O
on	O
a	O
single	O
chip	O
.	O
</s>
<s>
Sony/IBM/Toshiba	O
'	O
s	O
Cell	B-General_Concept
processor	O
,	O
a	O
nine-core	O
processor	O
with	O
one	O
general	O
purpose	O
PowerPC	B-Architecture
core	O
and	O
eight	O
specialized	O
SPUs	O
(	O
Synergistic	O
Processing	O
Unit	O
)	O
optimized	O
for	O
vector	B-Operating_System
operations	O
used	O
in	O
the	O
Sony	B-Operating_System
PlayStation	I-Operating_System
3	I-Operating_System
.	O
</s>
<s>
MAJC	B-General_Concept
5200	O
,	O
two-core	O
VLIW	B-General_Concept
processor	O
.	O
</s>
<s>
UltraSPARC	B-General_Concept
IV	I-General_Concept
and	O
UltraSPARC	B-General_Concept
IV+	I-General_Concept
,	O
dual-core	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
UltraSPARC	B-General_Concept
T1	I-General_Concept
,	O
an	O
eight-core	O
,	O
32-thread	O
processor	O
.	O
</s>
<s>
UltraSPARC	B-Device
T2	I-Device
,	O
an	O
eight-core	O
,	O
64-concurrent-thread	O
processor	O
.	O
</s>
<s>
UltraSPARC	B-Device
T3	I-Device
,	O
a	O
sixteen-core	O
,	O
128-concurrent-thread	O
processor	O
.	O
</s>
<s>
SPARC	B-Device
T4	I-Device
,	O
an	O
eight-core	O
,	O
64-concurrent-thread	O
processor	O
.	O
</s>
<s>
SPARC	B-Device
T5	I-Device
,	O
a	O
sixteen-core	O
,	O
128-concurrent-thread	O
processor	O
.	O
</s>
<s>
Sunway	B-General_Concept
SW26010	I-General_Concept
,	O
a	O
260-core	O
processor	O
used	O
in	O
the	O
Sunway	B-Device
TaihuLight	I-Device
.	O
</s>
<s>
TMS320C80	B-Architecture
MVP	I-Architecture
,	O
a	O
five-core	O
multimedia	O
video	O
processor	O
.	O
</s>
<s>
TILE64	B-General_Concept
,	O
a	O
64-core	O
32-bit	O
processor	O
.	O
</s>
<s>
TILE-Gx	B-General_Concept
,	O
a	O
72-core	O
64-bit	O
processor	O
.	O
</s>
<s>
XMOS	O
Software	O
Defined	O
Silicon	O
quad-core	B-Architecture
XS1-G4	O
.	O
</s>
<s>
The	O
research	O
and	O
development	O
of	O
multicore	B-Architecture
processors	I-Architecture
often	O
compares	O
many	O
options	O
,	O
and	O
benchmarks	O
are	O
developed	O
to	O
help	O
such	O
evaluations	O
.	O
</s>
