<s>
A	O
multi-chip	B-Algorithm
module	I-Algorithm
(	O
MCM	O
)	O
is	O
generically	O
an	O
electronic	O
assembly	O
(	O
such	O
as	O
a	O
package	O
with	O
a	O
number	O
of	O
conductor	O
terminals	O
or	O
"	O
pins	O
"	O
)	O
where	O
multiple	O
integrated	O
circuits	O
(	O
ICs	O
or	O
"	O
chips	O
"	O
)	O
,	O
semiconductor	O
dies	O
and/or	O
other	O
discrete	O
components	O
are	O
integrated	O
,	O
usually	O
onto	O
a	O
unifying	O
substrate	O
,	O
so	O
that	O
in	O
use	O
it	O
can	O
be	O
treated	O
as	O
if	O
it	O
were	O
a	O
larger	O
IC	O
.	O
</s>
<s>
Other	O
terms	O
for	O
MCM	O
packaging	O
include	O
"	O
heterogeneous	B-Algorithm
integration	I-Algorithm
"	O
or	O
"	O
hybrid	O
integrated	O
circuit	O
"	O
.	O
</s>
<s>
Multi-chip	B-Algorithm
modules	I-Algorithm
come	O
in	O
a	O
variety	O
of	O
forms	O
depending	O
on	O
the	O
complexity	O
and	O
development	O
philosophies	O
of	O
their	O
designers	O
.	O
</s>
<s>
Examples	O
of	O
this	O
include	O
implementations	O
of	O
IBM	O
's	O
POWER5	B-Device
and	O
Intel	O
's	O
Core	O
2	O
Quad	O
.	O
</s>
<s>
In	O
the	O
case	O
of	O
POWER5	B-Device
,	O
multiple	O
POWER5	B-Device
processors	O
and	O
their	O
associated	O
off-die	O
L3	O
cache	O
are	O
used	O
to	O
build	O
the	O
final	O
package	O
.	O
</s>
<s>
Since	O
area	O
is	O
more	O
often	O
at	O
a	O
premium	O
in	O
miniature	O
electronics	O
designs	O
,	O
the	O
chip-stack	O
is	O
an	O
attractive	O
option	O
in	O
many	O
applications	O
such	O
as	O
cell	O
phones	O
and	O
personal	B-Application
digital	I-Application
assistants	I-Application
(	O
PDAs	B-Application
)	O
.	O
</s>
<s>
With	O
the	O
use	O
of	O
a	O
3D	B-Architecture
integrated	I-Architecture
circuit	I-Architecture
and	O
a	O
thinning	O
process	O
,	O
as	O
many	O
as	O
ten	O
dies	O
can	O
be	O
stacked	O
to	O
create	O
a	O
high	O
capacity	O
SD	B-Device
memory	I-Device
card	I-Device
.	O
</s>
<s>
The	O
possible	O
way	O
to	O
increasing	O
the	O
performance	O
of	O
data	O
transfer	O
in	O
the	O
Chip	O
stack	O
is	O
use	O
Wireless	O
Networks	B-Architecture
on	I-Architecture
Chip	I-Architecture
(	O
WiNoC	O
)	O
.	O
</s>
<s>
Nintendo	O
's	O
Wii	B-Device
U	I-Device
Espresso	B-Device
(	O
microprocessor	O
)	O
has	O
its	O
CPU	O
,	O
GPU	B-Architecture
,	O
and	O
onboard	O
VRAM	O
(	O
integrated	O
into	O
the	O
GPU	B-Architecture
)	O
on	O
one	O
MCM	O
.	O
</s>
<s>
Samsung	B-Application
MCP	O
solutions	O
combining	O
mobile	O
DRAM	O
and	O
NAND	O
storage	O
.	O
</s>
<s>
AMD	B-Operating_System
Instinct	I-Operating_System
MI	O
series	O
GPUs	B-Architecture
based	O
on	O
CDNA	O
2	O
architecture	O
are	O
MCMs	O
of	O
one	O
or	O
two	O
graphics	O
compute	O
die	O
(	O
GCD	O
)	O
chips	O
.	O
</s>
<s>
AMD	O
Radeon	B-Device
RX	I-Device
7000	I-Device
series	I-Device
GPUs	B-Architecture
based	O
on	O
RDNA	O
3	O
architecture	O
are	O
MCMs	O
with	O
one	O
GCD	O
and	O
up	O
to	O
six	O
memory	O
cache	O
die	O
(	O
MCD	O
)	O
chips	O
.	O
</s>
