<s>
In	O
the	O
fields	O
of	O
digital	O
electronics	O
and	O
computer	B-Architecture
hardware	I-Architecture
,	O
multi-channel	B-Architecture
memory	I-Architecture
architecture	I-Architecture
is	O
a	O
technology	O
that	O
increases	O
the	O
data	O
transfer	O
rate	O
between	O
the	O
DRAM	O
memory	O
and	O
the	O
memory	B-General_Concept
controller	I-General_Concept
by	O
adding	O
more	O
channels	O
of	O
communication	O
between	O
them	O
.	O
</s>
<s>
Dual-channel	B-Architecture
memory	I-Architecture
employs	O
two	O
channels	O
.	O
</s>
<s>
The	O
technique	O
goes	O
back	O
as	O
far	O
as	O
the	O
1960s	O
having	O
been	O
used	O
in	O
IBM	B-Device
System/360	I-Device
Model	I-Device
91	I-Device
and	O
in	O
CDC	B-Device
6600	I-Device
.	O
</s>
<s>
Modern	O
high-end	O
desktop	O
and	O
workstation	O
processors	O
such	O
as	O
the	O
AMD	O
Ryzen	O
Threadripper	O
series	O
and	O
the	O
Intel	B-Device
Core	I-Device
i9	I-Device
Extreme	O
Edition	O
lineup	O
support	O
quad-channel	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
Server	O
processors	O
from	O
the	O
AMD	O
Epyc	O
series	O
and	O
the	O
Intel	B-Device
Xeon	I-Device
platforms	O
give	O
support	O
to	O
memory	O
bandwidth	O
starting	O
from	O
quad-channel	B-Architecture
module	O
layout	O
to	O
up	O
to	O
octa-channel	O
layout	O
.	O
</s>
<s>
In	O
March	O
2010	O
,	O
AMD	O
released	O
Socket	O
G34	O
and	O
Magny-Cours	O
Opteron	O
6100	O
series	O
processors	O
with	O
support	O
for	O
quad-channel	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
In	O
2006	O
,	O
Intel	O
released	O
chipsets	O
that	O
support	O
quad-channel	B-Architecture
memory	I-Architecture
for	O
its	O
LGA771	B-Device
platform	O
and	O
later	O
in	O
2011	O
for	O
its	O
LGA2011	B-Device
platform	O
.	O
</s>
<s>
Microcomputer	O
chipsets	O
with	O
even	O
more	O
channels	O
were	O
designed	O
;	O
for	O
example	O
,	O
the	O
chipset	O
in	O
the	O
AlphaStation	B-Device
600	O
(	O
1995	O
)	O
supports	O
eight-channel	O
memory	O
,	O
but	O
the	O
backplane	B-Architecture
of	O
the	O
machine	O
limited	O
operation	O
to	O
four	O
channels	O
.	O
</s>
<s>
Dual-channel-enabled	O
memory	B-General_Concept
controllers	I-General_Concept
in	O
a	O
PC	O
system	O
architecture	O
use	O
two	O
64-bit	O
data	O
channels	O
.	O
</s>
<s>
Dual-channel	B-Architecture
should	O
not	O
be	O
confused	O
with	O
double	O
data	O
rate	O
(	O
DDR	O
)	O
,	O
in	O
which	O
data	O
exchange	O
happens	O
twice	O
per	O
DRAM	O
clock	O
.	O
</s>
<s>
The	O
two	O
technologies	O
are	O
independent	O
of	O
each	O
other	O
,	O
and	O
many	O
motherboards	O
use	O
both	O
by	O
using	O
DDR	O
memory	O
in	O
a	O
dual-channel	B-Architecture
configuration	O
.	O
</s>
<s>
Dual-channel	B-Architecture
architecture	O
requires	O
a	O
dual-channel-capable	O
motherboard	O
and	O
two	O
or	O
more	O
DDR	O
,	O
DDR2	O
,	O
DDR3	O
,	O
DDR4	O
,	O
or	O
DDR5	O
memory	O
modules	O
.	O
</s>
<s>
Modules	O
rated	O
at	O
different	O
speeds	O
can	O
be	O
run	O
in	O
dual-channel	B-Architecture
mode	O
,	O
although	O
the	O
motherboard	O
will	O
then	O
run	O
all	O
memory	O
modules	O
at	O
the	O
speed	O
of	O
the	O
slowest	O
module	O
.	O
</s>
<s>
Some	O
motherboards	O
,	O
however	O
,	O
have	O
compatibility	O
issues	O
with	O
certain	O
brands	O
or	O
models	O
of	O
memory	O
when	O
attempting	O
to	O
use	O
them	O
in	O
dual-channel	B-Architecture
mode	O
.	O
</s>
<s>
Certain	O
Intel	O
chipsets	O
support	O
different	O
capacity	O
chips	O
in	O
what	O
they	O
call	O
Flex	O
Mode	O
:	O
the	O
capacity	O
that	O
can	O
be	O
matched	O
is	O
run	O
in	O
dual-channel	B-Architecture
,	O
while	O
the	O
remainder	O
runs	O
in	O
single-channel	O
.	O
</s>
<s>
Dual-channel	B-Architecture
architecture	O
is	O
a	O
technology	O
implemented	O
on	O
motherboards	O
by	O
the	O
motherboard	O
manufacturer	O
and	O
does	O
not	O
apply	O
to	O
memory	O
modules	O
.	O
</s>
<s>
Theoretically	O
any	O
matched	O
pair	O
of	O
memory	O
modules	O
may	O
be	O
used	O
in	O
either	O
single	O
-	O
or	O
dual-channel	B-Architecture
operation	O
,	O
provided	O
the	O
motherboard	O
supports	O
this	O
architecture	O
.	O
</s>
<s>
Theoretically	O
,	O
dual-channel	B-Architecture
configurations	O
double	O
the	O
memory	O
bandwidth	O
when	O
compared	O
to	O
single-channel	O
configurations	O
.	O
</s>
<s>
A	O
benchmark	O
performed	O
by	O
TweakTown	O
,	O
using	O
SiSoftware	O
Sandra	O
,	O
measured	O
around	O
70%	O
increase	O
in	O
performance	O
of	O
a	O
quadruple-channel	O
configuration	O
,	O
when	O
compared	O
to	O
a	O
dual-channel	B-Architecture
configuration	O
.	O
</s>
<s>
Dual-channel	B-Architecture
was	O
originally	O
conceived	O
as	O
a	O
way	O
to	O
maximize	O
memory	O
throughput	O
by	O
combining	O
two	O
64-bit	O
buses	O
into	O
a	O
single	O
128-bit	O
bus	O
.	O
</s>
<s>
However	O
,	O
due	O
to	O
lackluster	O
performance	O
gains	O
in	O
consumer	O
applications	O
,	O
more	O
modern	O
implementations	O
of	O
dual-channel	B-Architecture
use	O
the	O
"	O
unganged	O
"	O
mode	O
by	O
default	O
,	O
which	O
maintains	O
two	O
64-bit	O
memory	O
buses	O
but	O
allows	O
independent	O
access	O
to	O
each	O
channel	O
,	O
in	O
support	O
of	O
multithreading	B-General_Concept
with	O
multi-core	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
With	O
RAID0	O
(	O
which	O
is	O
analogous	O
to	O
"	O
ganged	O
"	O
mode	O
)	O
,	O
it	O
is	O
up	O
to	O
the	O
additional	O
logic	O
layer	O
to	O
provide	O
better	O
(	O
ideally	O
even	O
)	O
usage	O
of	O
all	O
available	O
hardware	B-Architecture
units	O
(	O
storage	O
devices	O
,	O
or	O
memory	O
modules	O
)	O
and	O
increased	O
overall	O
performance	O
.	O
</s>
<s>
On	O
the	O
other	O
hand	O
,	O
with	O
JBOD	O
(	O
which	O
is	O
analogous	O
to	O
"	O
unganged	O
"	O
mode	O
)	O
it	O
is	O
relied	O
on	O
the	O
statistical	O
usage	O
patterns	O
to	O
ensure	O
increased	O
overall	O
performance	O
through	O
even	O
usage	O
of	O
all	O
available	O
hardware	B-Architecture
units	O
.	O
</s>
<s>
DDR3	O
triple-channel	B-Architecture
architecture	O
is	O
used	O
in	O
the	O
Intel	O
Core	O
i7-900	O
series	O
(	O
the	O
Intel	O
Core	O
i7-800	O
series	O
only	O
support	O
up	O
to	O
dual-channel	B-Architecture
)	O
.	O
</s>
<s>
Intel	O
X58	O
)	O
supports	O
DDR3	O
triple-channel	B-Architecture
,	O
normally	O
1333	O
and	O
1600Mhz	O
,	O
but	O
can	O
run	O
at	O
higher	O
clock	O
speeds	O
on	O
certain	O
motherboards	O
.	O
</s>
<s>
AMD	O
Socket	O
AM3	O
processors	O
do	O
not	O
use	O
the	O
DDR3	O
triple-channel	B-Architecture
architecture	O
but	O
instead	O
use	O
dual-channel	B-Architecture
DDR3	O
memory	O
.	O
</s>
<s>
The	O
same	O
applies	O
to	O
the	O
Intel	O
Core	O
i3	O
,	O
Core	B-Device
i5	I-Device
and	O
Core	O
i7-800	O
series	O
,	O
which	O
are	O
used	O
on	O
the	O
LGA	B-Device
1156	I-Device
platforms	O
(	O
e.g.	O
,	O
Intel	B-Device
P55	I-Device
)	O
.	O
</s>
<s>
According	O
to	O
Intel	O
,	O
a	O
Core	B-Device
i7	I-Device
with	O
DDR3	O
operating	O
at	O
1066MHz	O
will	O
offer	O
peak	O
data	O
transfer	O
rates	O
of	O
25.6GB/s	O
when	O
operating	O
in	O
triple-channel	B-Architecture
interleaved	B-General_Concept
mode	O
.	O
</s>
<s>
When	O
operating	O
in	O
triple-channel	B-Architecture
mode	O
,	O
memory	B-General_Concept
latency	I-General_Concept
is	O
reduced	O
due	O
to	O
interleaving	O
,	O
meaning	O
that	O
each	O
module	O
is	O
accessed	O
sequentially	O
for	O
smaller	O
bits	O
of	O
data	O
rather	O
than	O
completely	O
filling	O
up	O
one	O
module	O
before	O
accessing	O
the	O
next	O
one	O
.	O
</s>
<s>
When	O
two	O
memory	O
modules	O
are	O
installed	O
,	O
the	O
architecture	O
will	O
operate	O
in	O
dual-channel	B-Architecture
architecture	O
mode	O
.	O
</s>
<s>
Intel	B-Device
Core	I-Device
i7	I-Device
:	O
</s>
<s>
Intel	B-Device
Xeon	I-Device
:	O
</s>
<s>
Quad-channel	B-Architecture
memory	I-Architecture
debuted	O
on	O
Intel	O
's	O
Nehalem-EX	O
LGA	B-Device
1567	I-Device
platform	O
of	O
Xeon	B-Device
CPUs	O
,	O
aka	O
Beckton	O
in	O
2010	O
,	O
and	O
was	O
introduced	O
to	O
the	O
high	O
end	O
product	O
line	O
on	O
the	O
Intel	B-Device
X79	I-Device
LGA	B-Device
2011	I-Device
platform	O
with	O
Sandy	O
Bridge-E	O
in	O
late	O
2011	O
.	O
</s>
<s>
DDR4	O
replaced	O
DDR3	O
on	O
the	O
Intel	B-Device
X99	I-Device
LGA	B-Device
2011	I-Device
platform	O
,	O
aka	O
Haswell-E	O
,	O
and	O
is	O
also	O
used	O
in	O
AMD	O
's	O
Threadripper	O
platform	O
.	O
</s>
<s>
DDR3	O
quad-channel	B-Architecture
architecture	O
is	O
used	O
in	O
the	O
AMD	O
G34	O
platform	O
and	O
in	O
the	O
aforementioned	O
Intel	O
CPUs	O
prior	O
to	O
Haswell	O
.	O
</s>
<s>
AMD	O
processors	O
for	O
the	O
C32	O
platform	O
and	O
Intel	O
processors	O
for	O
the	O
LGA	B-Device
1155	I-Device
platform	O
(	O
e.g.	O
</s>
<s>
Intel	O
Z68	O
)	O
use	O
dual-channel	B-Architecture
DDR3	O
memory	O
instead	O
.	O
</s>
<s>
The	O
architecture	O
can	O
be	O
used	O
only	O
when	O
all	O
four	O
memory	O
modules	O
(	O
or	O
a	O
multiple	O
of	O
four	O
)	O
are	O
identical	O
in	O
capacity	O
and	O
speed	O
,	O
and	O
are	O
placed	O
in	O
quad-channel	B-Architecture
slots	O
.	O
</s>
<s>
When	O
two	O
memory	O
modules	O
are	O
installed	O
,	O
the	O
architecture	O
will	O
operate	O
in	O
a	O
dual-channel	B-Architecture
mode	O
;	O
When	O
three	O
memory	O
modules	O
are	O
installed	O
,	O
the	O
architecture	O
will	O
operate	O
in	O
a	O
triple-channel	B-Architecture
mode	O
.	O
</s>
<s>
Intel	B-Device
Xeon	I-Device
:	O
</s>
<s>
Supported	O
by	O
Qualcomm	O
Centriq	O
server	O
processors	O
,	O
and	O
processors	O
from	O
the	O
Intel	B-Device
Xeon	I-Device
Scalable	O
platform	O
.	O
</s>
