<s>
The	O
68HC12	B-Device
(	O
6812	O
or	O
HC12	B-Device
for	O
short	O
)	O
is	O
a	O
microcontroller	B-Architecture
family	O
from	O
Freescale	O
Semiconductor	O
.	O
</s>
<s>
Originally	O
introduced	O
in	O
the	O
mid-1990s	O
,	O
the	O
architecture	O
is	O
an	O
enhancement	O
of	O
the	O
Freescale	B-Device
68HC11	I-Device
.	O
</s>
<s>
Programs	O
written	O
for	O
the	O
HC11	B-Device
are	O
usually	O
compatible	O
with	O
the	O
HC12	B-Device
,	O
which	O
has	O
a	O
few	O
extra	O
instructions	B-General_Concept
.	O
</s>
<s>
The	O
first	O
68HC12	B-Device
derivatives	O
had	O
a	O
maximum	O
bus	O
speed	O
of	O
8MHz	O
and	O
flash	B-Device
memory	I-Device
sizes	O
up	O
to	O
128KB	O
.	O
</s>
<s>
Like	O
the	O
68HC11	B-Device
,	O
the	O
68HC12	B-Device
has	O
two	O
8-bit	O
accumulators	O
A	O
and	O
B	O
(	O
referred	O
to	O
as	O
a	O
single	O
16-bit	B-Device
accumulator	O
,	O
D	O
,	O
when	O
A	O
&	O
B	O
are	O
cascaded	O
so	O
as	O
to	O
allow	O
for	O
operations	O
involving	O
16bits	O
)	O
,	O
two	O
16-bit	B-Device
registers	O
X	O
and	O
Y	O
,	O
a	O
16-bit	B-Device
program	O
counter	O
,	O
a	O
16-bit	B-Device
stack	O
pointer	O
and	O
an	O
8-bit	O
Condition	B-General_Concept
Code	I-General_Concept
Register	I-General_Concept
.	O
</s>
<s>
The	O
68HC12	B-Device
adds	O
to	O
and	O
replaces	O
a	O
small	O
number	O
of	O
68HC11	B-Device
instructions	B-General_Concept
with	O
new	O
forms	O
that	O
are	O
closer	O
to	O
the	O
6809	B-Device
processor	O
.	O
</s>
<s>
More	O
significantly	O
it	O
changes	O
the	O
instruction	O
encodings	O
to	O
be	O
far	O
more	O
dense	O
and	O
adds	O
many	O
6809	B-Device
like	O
indexing	O
features	O
,	O
some	O
with	O
even	O
more	O
flexibility	O
.	O
</s>
<s>
The	O
was	O
introduced	O
by	O
Freescale	O
in	O
September	O
2004	O
,	O
claiming	O
to	O
be	O
the	O
"	O
industry	O
's	O
first	O
single-chip	O
fast-Ethernet	O
Flash	O
microcontroller.	O
"	O
</s>
<s>
It	O
features	O
a	O
25MHz	O
HCS12	B-Device
CPU	O
,	O
64KB	O
of	O
FLASH	B-Device
EEPROM	I-Device
,	O
8KB	O
of	O
RAM	B-Architecture
,	O
and	O
an	O
Ethernet	O
10/100Mbit/s	O
controller	O
.	O
</s>
<s>
The	O
CPU	O
of	O
the	O
S12X	O
derivative	O
also	O
features	O
several	O
new	O
instructions	B-General_Concept
to	O
increase	O
performance	O
.	O
</s>
<s>
Freescale	O
announced	O
the	O
in	O
May	O
2006	O
to	O
further	O
extend	O
the	O
S12X	O
family	O
to	O
50MHz	O
bus	O
speed	O
and	O
add	O
a	O
Memory	B-General_Concept
protection	I-General_Concept
unit	O
(	O
based	O
on	O
segmentation	B-General_Concept
)	O
and	O
a	O
hardware	O
scheme	O
to	O
provide	O
emulated	O
EEPROM	B-General_Concept
.	O
</s>
<s>
HCS12	B-Device
products	O
contain	O
a	O
single	O
processor	O
,	O
the	O
HCS12X	O
feature	O
the	O
additional	O
XGATE	O
peripheral	O
processor	O
.	O
</s>
<s>
The	O
XGATE	O
co-processor	O
is	O
a	O
16-bit	B-Device
RISC	O
processor	O
operating	O
at	O
twice	O
the	O
main	O
bus	O
clock	O
.	O
</s>
<s>
Typically	O
the	O
XGATE	O
code	O
is	O
copied	O
to	O
RAM	B-Architecture
at	O
device	O
startup	O
and	O
then	O
executed	O
from	O
RAM	B-Architecture
for	O
a	O
speed	O
benefit	O
.	O
</s>
<s>
The	O
registers	O
share	O
addresses	O
,	O
but	O
the	O
flash	O
and	O
RAM	B-Architecture
appear	O
at	O
different	O
addresses	O
between	O
the	O
cores	O
.	O
</s>
