<s>
Montecito	B-Device
is	O
the	O
code-name	O
of	O
a	O
major	O
release	O
of	O
Intel	O
's	O
Itanium	B-General_Concept
2	I-General_Concept
Processor	B-General_Concept
Family	O
(	O
IPF	O
)	O
,	O
which	O
implements	O
the	O
Intel	B-General_Concept
Itanium	I-General_Concept
architecture	O
on	O
a	O
dual-core	B-Architecture
processor	I-Architecture
.	O
</s>
<s>
It	O
was	O
officially	O
launched	O
by	O
Intel	O
on	O
July	O
18	O
,	O
2006	O
as	O
the	O
"	O
Dual-Core	B-Architecture
Intel	B-General_Concept
Itanium	I-General_Concept
2	O
processor	B-General_Concept
"	O
.	O
</s>
<s>
According	O
to	O
Intel	O
,	O
Montecito	B-Device
doubles	O
performance	O
versus	O
the	O
previous	O
,	O
single-core	O
Itanium	B-General_Concept
2	I-General_Concept
processor	B-General_Concept
,	O
and	O
reduces	O
power	O
consumption	O
by	O
about	O
20%	O
.	O
</s>
<s>
2-way	O
coarse-grained	O
multithreading	B-General_Concept
per	O
core	O
(	O
not	O
simultaneous	O
)	O
.	O
</s>
<s>
Montecito-flavour	O
of	O
multi-threading	O
is	O
dubbed	O
temporal	O
,	O
or	O
TMT	O
.	O
</s>
<s>
This	O
is	O
also	O
known	O
as	O
switch-on-event	O
multithreading	B-General_Concept
,	O
or	O
SoEMT	O
.	O
</s>
<s>
The	O
two	O
separate	O
threads	O
do	O
not	O
run	O
simultaneously	O
,	O
but	O
the	O
core	O
switches	O
thread	O
in	O
case	O
of	O
a	O
high	O
latency	O
event	O
,	O
like	O
an	O
L3	O
cache	B-General_Concept
miss	I-General_Concept
which	O
would	O
otherwise	O
stall	O
execution	O
.	O
</s>
<s>
1.72	O
billion	O
transistors	B-Application
per	O
die	O
,	O
which	O
is	O
added	O
up	O
from	O
:	O
</s>
<s>
Lower	O
power	O
consumption	O
and	O
thermal	O
dissipation	O
than	O
earlier	O
flagship	O
Itaniums	B-General_Concept
,	O
despite	O
the	O
high	O
transistor	B-Application
count	O
;	O
75-104	O
W	O
.	O
This	O
is	O
mainly	O
achieved	O
by	O
applying	O
different	O
types	O
of	O
transistors	B-Application
.	O
</s>
<s>
By	O
default	O
,	O
slower	O
and	O
low-leakage	O
transistors	B-Application
were	O
used	O
,	O
while	O
high-speed	O
,	O
thus	O
high-leakage	O
ones	O
where	O
it	O
was	O
necessary	O
.	O
</s>
<s>
Improved	O
,	O
higher	O
bandwidth	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
(	O
FSB	O
)	O
,	O
with	O
three	O
times	O
the	O
capacity	O
of	O
the	O
existing	O
bus	B-General_Concept
design	O
.	O
</s>
<s>
System	O
throughput	O
per	O
node	O
should	O
be	O
at	O
least	O
21	O
GB/s	O
,	O
which	O
suggest	O
dual	O
333.333MHz	O
(	O
double	O
pumped	O
,	O
resulting	O
2×667	O
effective	O
MHz	O
)	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
.	O
</s>
<s>
However	O
,	O
it	O
is	O
up	O
to	O
system	O
integrators	O
how	O
they	O
organize	O
their	O
bus	B-General_Concept
topology	O
.	O
</s>
<s>
All	O
Montecito	B-Device
processors	O
support	O
533MHz	O
/	O
400MHz	O
FSB	O
speed	O
.	O
</s>
<s>
Also	O
available	O
with	O
legacy	B-Device
FSB	O
for	O
upgrading	B-General_Concept
existing	O
system	O
designs	O
.	O
</s>
<s>
Eliminates	O
the	O
hardware-based	O
x86	B-Operating_System
instruction	O
emulation	O
circuitry	O
,	O
in	O
favor	O
of	O
the	O
more	O
efficient	O
software-based	O
IA-32	B-Device
Execution	I-Device
Layer	I-Device
.	O
</s>
<s>
On	O
October	O
25	O
,	O
2005	O
Intel	O
announced	O
that	O
the	O
first	O
dual-core	B-Architecture
Itanium	B-General_Concept
processor	B-General_Concept
would	O
be	O
delayed	O
until	O
"	O
the	O
middle	O
of	O
next	O
year.	O
"	O
</s>
<s>
Montecito	B-Device
was	O
launched	O
on	O
July	O
18	O
,	O
2006	O
.	O
</s>
<s>
Due	O
to	O
unspecified	O
issues	O
,	O
Intel	O
's	O
Foxton	B-Device
power	I-Device
management	I-Device
technology	I-Device
was	O
disabled	O
in	O
the	O
first	O
release	O
of	O
Montecito	B-Device
,	O
and	O
the	O
front-side	B-Architecture
bus	I-Architecture
frequency	O
was	O
reduced	O
to	O
267MHz	O
(	O
533.333MHz	O
effective	O
)	O
instead	O
of	O
the	O
333MHz	O
speed	O
originally	O
scheduled	O
for	O
the	O
design	O
 [ 3 ] 	O
.	O
</s>
<s>
There	O
are	O
no	O
plans	O
for	O
additional	O
Montecito	B-Device
processors	O
;	O
the	O
successor	O
,	O
Montvale	B-General_Concept
was	O
released	O
in	O
late	O
2007	O
.	O
</s>
