<s>
The	O
modified	B-Device
Harvard	I-Device
architecture	I-Device
is	O
a	O
variation	O
of	O
the	O
Harvard	B-Architecture
computer	I-Architecture
architecture	I-Architecture
that	O
,	O
unlike	O
the	O
pure	O
Harvard	B-Architecture
architecture	I-Architecture
,	O
allows	O
the	O
contents	O
of	O
the	O
instruction	O
memory	O
to	O
be	O
accessed	O
as	O
data	O
.	O
</s>
<s>
Most	O
modern	O
computers	O
that	O
are	O
documented	O
as	O
Harvard	B-Architecture
architecture	I-Architecture
are	O
,	O
in	O
fact	O
,	O
modified	B-Device
Harvard	I-Device
architecture	I-Device
.	O
</s>
<s>
The	O
original	O
Harvard	B-Architecture
architecture	I-Architecture
computer	O
,	O
the	O
Harvard	B-Device
Mark	I-Device
I	I-Device
,	O
employed	O
entirely	O
separate	O
memory	O
systems	O
to	O
store	O
instructions	O
and	O
data	O
.	O
</s>
<s>
The	O
CPU	B-Device
fetched	O
the	O
next	O
instruction	O
and	O
loaded	O
or	O
stored	O
data	O
simultaneously	O
and	O
independently	O
.	O
</s>
<s>
This	O
is	O
in	O
contrast	O
to	O
a	O
von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
computer	O
,	O
in	O
which	O
both	O
instructions	O
and	O
data	O
are	O
stored	O
in	O
the	O
same	O
memory	O
system	O
and	O
(	O
without	O
the	O
complexity	O
of	O
a	O
CPU	B-General_Concept
cache	I-General_Concept
)	O
must	O
be	O
accessed	O
in	O
turn	O
.	O
</s>
<s>
The	O
physical	O
separation	O
of	O
instruction	O
and	O
data	O
memory	O
is	O
sometimes	O
held	O
to	O
be	O
the	O
distinguishing	O
feature	O
of	O
modern	O
Harvard	B-Architecture
architecture	I-Architecture
computers	O
.	O
</s>
<s>
With	O
microcontrollers	B-Architecture
(	O
entire	O
computer	O
systems	O
integrated	O
onto	O
single	O
chips	O
)	O
,	O
the	O
use	O
of	O
different	O
memory	O
technologies	O
for	O
instructions	O
(	O
e.g.	O
</s>
<s>
flash	B-Device
memory	I-Device
)	O
and	O
data	O
(	O
typically	O
read/write	B-General_Concept
memory	I-General_Concept
)	O
in	O
von	O
Neumann	O
machines	O
is	O
becoming	O
popular	O
.	O
</s>
<s>
The	O
true	O
distinction	O
of	O
a	O
Harvard	O
machine	O
is	O
that	O
instruction	O
and	O
data	O
memory	O
occupy	O
different	O
address	B-General_Concept
spaces	I-General_Concept
.	O
</s>
<s>
A	O
computer	O
with	O
a	O
von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
has	O
the	O
advantage	O
over	O
pure	O
Harvard	O
machines	O
in	O
that	O
code	O
can	O
also	O
be	O
accessed	O
and	O
treated	O
the	O
same	O
as	O
data	O
,	O
and	O
vice	O
versa	O
.	O
</s>
<s>
This	O
allows	O
,	O
for	O
example	O
,	O
data	O
to	O
be	O
read	O
from	O
disk	B-Device
storage	I-Device
into	O
memory	O
and	O
then	O
executed	O
as	O
code	O
,	O
or	O
self-optimizing	O
software	O
systems	O
using	O
technologies	O
such	O
as	O
just-in-time	O
compilation	O
to	O
write	O
machine	O
code	O
into	O
their	O
own	O
memory	O
and	O
then	O
later	O
execute	O
it	O
.	O
</s>
<s>
Another	O
example	O
is	O
self-modifying	B-Application
code	I-Application
,	O
which	O
allows	O
a	O
program	O
to	O
modify	O
itself	O
.	O
</s>
<s>
Most	O
modern	O
computers	O
instead	O
implement	O
a	O
modified	B-Device
Harvard	I-Device
architecture	I-Device
.	O
</s>
<s>
Those	O
modifications	O
are	O
various	O
ways	O
to	O
loosen	O
the	O
strict	O
separation	O
between	O
code	O
and	O
data	O
,	O
while	O
still	O
supporting	O
the	O
higher	O
performance	O
concurrent	O
data	O
and	O
instruction	O
access	O
of	O
the	O
Harvard	B-Architecture
architecture	I-Architecture
.	O
</s>
<s>
The	O
most	O
common	O
modification	O
builds	O
a	O
memory	B-General_Concept
hierarchy	I-General_Concept
with	O
separate	O
CPU	B-General_Concept
caches	I-General_Concept
for	O
instructions	O
and	O
data	O
at	O
lower	O
levels	O
of	O
the	O
hierarchy	O
.	O
</s>
<s>
There	O
is	O
a	O
single	O
address	B-General_Concept
space	I-General_Concept
for	O
instructions	O
and	O
data	O
,	O
providing	O
the	O
von	B-Architecture
Neumann	I-Architecture
model	I-Architecture
,	O
but	O
the	O
CPU	B-Device
fetches	O
instructions	O
from	O
the	O
instruction	O
cache	O
and	O
fetches	O
data	O
from	O
the	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Most	O
programmers	O
never	O
need	O
to	O
be	O
aware	O
of	O
the	O
fact	O
that	O
the	O
processor	O
core	O
implements	O
a	O
(	O
modified	O
)	O
Harvard	B-Architecture
architecture	I-Architecture
,	O
although	O
they	O
benefit	O
from	O
its	O
speed	O
advantages	O
.	O
</s>
<s>
Only	O
programmers	O
who	O
generate	O
and	O
store	O
instructions	O
into	O
memory	O
need	O
to	O
be	O
aware	O
of	O
issues	O
such	O
as	O
cache	B-General_Concept
coherency	I-General_Concept
,	O
if	O
the	O
store	O
does	O
n't	O
modify	O
or	O
invalidate	O
a	O
cached	O
copy	O
of	O
the	O
instruction	O
in	O
an	O
instruction	O
cache	O
.	O
</s>
<s>
Another	O
change	O
preserves	O
the	O
"	O
separate	O
address	B-General_Concept
space	I-General_Concept
"	O
nature	O
of	O
a	O
Harvard	O
machine	O
,	O
but	O
provides	O
special	O
machine	O
operations	O
to	O
access	O
the	O
contents	O
of	O
the	O
instruction	O
memory	O
as	O
data	O
.	O
</s>
<s>
Because	O
data	O
is	O
not	O
directly	O
executable	O
as	O
instructions	O
,	O
such	O
machines	O
are	O
not	O
always	O
viewed	O
as	O
"	O
modified	O
"	O
Harvard	B-Architecture
architecture	I-Architecture
:	O
</s>
<s>
Write	O
access	O
:	O
a	O
capability	O
for	O
reprogramming	O
is	O
generally	O
required	O
;	O
few	O
computers	O
are	O
purely	O
ROM-based	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
microcontroller	B-Architecture
usually	O
has	O
operations	O
to	O
write	O
to	O
the	O
flash	B-Device
memory	I-Device
used	O
to	O
hold	O
its	O
instructions	O
.	O
</s>
<s>
EEPROM/PROM	O
replacement	O
is	O
an	O
alternative	O
method	O
.	O
</s>
<s>
A	O
few	O
Harvard	B-Architecture
architecture	I-Architecture
processors	O
,	O
such	O
as	O
the	O
Maxim	O
Integrated	O
MAXQ	O
,	O
can	O
execute	O
instructions	O
fetched	O
from	O
any	O
memory	O
segment	O
unlike	O
the	O
original	O
Harvard	O
processor	O
,	O
which	O
can	O
only	O
execute	O
instructions	O
fetched	O
from	O
the	O
program	B-Device
memory	I-Device
segment	O
.	O
</s>
<s>
Such	O
processors	O
,	O
like	O
other	O
Harvard	B-Architecture
architecture	I-Architecture
processors	O
and	O
unlike	O
pure	O
von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
can	O
read	O
an	O
instruction	O
and	O
read	O
a	O
data	O
value	O
simultaneously	O
,	O
if	O
they	O
're	O
in	O
separate	O
memory	O
segments	O
,	O
since	O
the	O
processor	O
has	O
(	O
at	O
least	O
)	O
two	O
separate	O
memory	O
segments	O
with	O
independent	O
data	O
buses	O
.	O
</s>
<s>
The	O
most	O
obvious	O
programmer-visible	O
difference	O
between	O
this	O
kind	O
of	O
modified	B-Device
Harvard	I-Device
architecture	I-Device
and	O
a	O
pure	O
von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
is	O
that	O
when	O
executing	O
an	O
instruction	O
from	O
one	O
memory	O
segment	O
the	O
same	O
memory	O
segment	O
cannot	O
be	O
simultaneously	O
accessed	O
as	O
data	O
.	O
</s>
<s>
By	O
contrast	O
,	O
von	O
Neumann	O
and	O
split-cache	O
modified	O
Harvard	O
machines	O
store	O
both	O
instructions	O
and	O
data	O
in	O
a	O
single	O
address	B-General_Concept
space	I-General_Concept
,	O
so	O
address	O
"	O
zero	O
"	O
refers	O
to	O
only	O
one	O
location	O
and	O
whether	O
the	O
binary	O
pattern	O
in	O
that	O
location	O
is	O
interpreted	O
as	O
an	O
instruction	O
or	O
data	O
is	O
defined	O
by	O
how	O
the	O
program	O
is	O
written	O
.	O
</s>
<s>
However	O
,	O
just	O
like	O
pure	O
Harvard	O
machines	O
,	O
instruction-memory-as-data	O
modified	O
Harvard	O
machines	O
have	O
separate	O
address	B-General_Concept
spaces	I-General_Concept
,	O
so	O
have	O
separate	O
addresses	O
"	O
zero	O
"	O
for	O
instruction	O
and	O
data	O
space	O
,	O
so	O
this	O
does	O
not	O
distinguish	O
that	O
type	O
of	O
modified	O
Harvard	O
machines	O
from	O
pure	O
Harvard	O
machines	O
.	O
</s>
<s>
This	O
is	O
the	O
point	O
of	O
pure	O
or	O
modified	O
Harvard	O
machines	O
,	O
and	O
why	O
they	O
co-exist	O
with	O
the	O
more	O
flexible	O
and	O
general	O
von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
:	O
separate	O
memory	O
pathways	O
to	O
the	O
CPU	B-Device
allow	O
instructions	O
to	O
be	O
fetched	O
and	O
data	O
to	O
be	O
accessed	O
at	O
the	O
same	O
time	O
,	O
improving	O
throughput	O
.	O
</s>
<s>
The	O
pure	O
Harvard	O
machines	O
have	O
separate	O
pathways	O
with	O
separate	O
address	B-General_Concept
spaces	I-General_Concept
.	O
</s>
<s>
Split-cache	O
modified	O
Harvard	O
machines	O
have	O
such	O
separate	O
access	O
paths	O
for	O
CPU	B-General_Concept
caches	I-General_Concept
or	O
other	O
tightly	O
coupled	O
memories	O
,	O
but	O
a	O
unified	O
access	O
path	O
covers	O
the	O
rest	O
of	O
the	O
memory	B-General_Concept
hierarchy	I-General_Concept
.	O
</s>
<s>
From	O
a	O
programmer	O
's	O
point	O
of	O
view	O
,	O
a	O
modified	O
Harvard	O
processor	O
in	O
which	O
instruction	O
and	O
data	O
memories	O
share	O
an	O
address	B-General_Concept
space	I-General_Concept
is	O
usually	O
treated	O
as	O
a	O
von	O
Neumann	O
machine	O
until	O
cache	B-General_Concept
coherency	I-General_Concept
becomes	O
an	O
issue	O
,	O
as	O
with	O
self-modifying	B-Application
code	I-Application
and	O
program	O
loading	O
.	O
</s>
<s>
This	O
can	O
be	O
confusing	O
,	O
but	O
such	O
issues	O
are	O
usually	O
visible	O
only	O
to	O
systems	B-Application
programmers	I-Application
and	O
integrators	O
.	O
</s>
<s>
The	O
original	O
Harvard	O
machine	O
,	O
the	O
Mark	B-Device
I	I-Device
,	O
stored	O
instructions	O
on	O
a	O
punched	O
paper	O
tape	O
and	O
data	O
in	O
electro-mechanical	O
counters	O
.	O
</s>
<s>
Today	O
a	O
Harvard	O
machine	O
such	O
as	O
the	O
PIC	B-Architecture
microcontroller	I-Architecture
might	O
use	O
12-bit	O
wide	O
flash	B-Device
memory	I-Device
for	O
instructions	O
,	O
and	O
8-bit	O
wide	O
SRAM	B-Architecture
for	O
data	O
.	O
</s>
<s>
In	O
contrast	O
,	O
a	O
von	O
Neumann	O
microcontroller	B-Architecture
such	O
as	O
an	O
ARM7TDMI	O
,	O
or	O
a	O
modified	O
Harvard	O
ARM9	O
core	O
,	O
necessarily	O
provides	O
uniform	O
access	O
to	O
flash	B-Device
memory	I-Device
and	O
SRAM	B-Architecture
(	O
as	O
8	O
bit	O
bytes	O
,	O
in	O
those	O
cases	O
)	O
.	O
</s>
<s>
Outside	O
of	O
applications	O
where	O
a	O
cacheless	O
DSP	B-Architecture
or	O
microcontroller	B-Architecture
is	O
required	O
,	O
most	O
modern	O
processors	O
have	O
a	O
CPU	B-General_Concept
cache	I-General_Concept
which	O
partitions	O
instruction	O
and	O
data	O
.	O
</s>
<s>
There	O
are	O
also	O
processors	O
which	O
are	O
Harvard	O
machines	O
by	O
the	O
most	O
rigorous	O
definition	O
(	O
that	O
program	O
and	O
data	O
memory	O
occupy	O
different	O
address	B-General_Concept
spaces	I-General_Concept
)	O
,	O
and	O
are	O
only	O
modified	O
in	O
the	O
weak	O
sense	O
that	O
there	O
are	O
operations	O
to	O
read	O
and/or	O
write	O
program	B-Device
memory	I-Device
as	O
data	O
.	O
</s>
<s>
For	O
example	O
,	O
LPM	O
(	O
Load	O
Program	B-Device
Memory	I-Device
)	O
and	O
SPM	O
(	O
Store	O
Program	B-Device
Memory	I-Device
)	O
instructions	O
in	O
the	O
Atmel	B-Architecture
AVR	I-Architecture
implement	O
such	O
a	O
modification	O
.	O
</s>
<s>
Similar	O
solutions	O
are	O
found	O
in	O
other	O
microcontrollers	B-Architecture
such	O
as	O
the	O
PIC	B-Architecture
and	O
Z8Encore	O
!,	O
many	O
families	O
of	O
digital	B-Architecture
signal	I-Architecture
processors	I-Architecture
such	O
as	O
the	O
TI	B-Architecture
C55x	I-Architecture
cores	I-Architecture
,	O
and	O
more	O
.	O
</s>
<s>
Because	O
instruction	O
execution	O
is	O
still	O
restricted	O
to	O
the	O
program	O
address	B-General_Concept
space	I-General_Concept
,	O
these	O
processors	O
are	O
very	O
unlike	O
von	O
Neumann	O
machines	O
.	O
</s>
<s>
External	O
wiring	O
can	O
also	O
convert	O
a	O
strictly	O
Harvard	O
CPU	B-Device
core	O
into	O
an	O
modified	O
Harvard	O
one	O
,	O
for	O
example	O
by	O
simply	O
combining	O
`PSEN#`	O
(	O
program	O
space	O
read	O
)	O
and	O
`RD#`	O
(	O
external	O
data	O
space	O
read	O
)	O
signals	O
externally	O
through	O
an	O
AND	O
gate	O
on	O
a	O
Intel	B-Architecture
8051	I-Architecture
family	O
microcontroller	B-Architecture
,	O
the	O
microcontroller	B-Architecture
are	O
said	O
to	O
be	O
"	O
von	O
Neumann	O
connected	O
,	O
"	O
as	O
the	O
external	O
data	O
and	O
program	O
address	B-General_Concept
spaces	I-General_Concept
become	O
unified	O
.	O
</s>
<s>
Having	O
separate	O
address	B-General_Concept
spaces	I-General_Concept
creates	O
certain	O
difficulties	O
in	O
programming	O
with	O
high-level	O
languages	O
that	O
do	O
not	O
directly	O
support	O
the	O
notion	O
that	O
tables	O
of	O
read-only	O
data	O
might	O
be	O
in	O
a	O
different	O
address	B-General_Concept
space	I-General_Concept
from	O
normal	O
writable	O
data	O
(	O
and	O
thus	O
need	O
to	O
be	O
read	O
using	O
different	O
instructions	O
)	O
.	O
</s>
<s>
The	O
C	B-Language
programming	I-Language
language	I-Language
can	O
support	O
multiple	O
address	B-General_Concept
spaces	I-General_Concept
either	O
through	O
non-standard	O
extensions	O
or	O
through	O
the	O
now	O
standardized	O
extensions	B-Language
to	I-Language
support	I-Language
embedded	I-Language
processors	I-Language
.	O
</s>
