<s>
In	O
computer	O
engineering	O
,	O
microarchitecture	B-General_Concept
,	O
also	O
called	O
computer	B-General_Concept
organization	I-General_Concept
and	O
sometimes	O
abbreviated	O
as	O
µarch	O
or	O
uarch	B-General_Concept
,	O
is	O
the	O
way	O
a	O
given	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	B-General_Concept
)	O
is	O
implemented	O
in	O
a	O
particular	O
processor	B-General_Concept
.	O
</s>
<s>
A	O
given	O
ISA	B-General_Concept
may	O
be	O
implemented	O
with	O
different	O
microarchitectures	B-General_Concept
;	O
implementations	O
may	O
vary	O
due	O
to	O
different	O
goals	O
of	O
a	O
given	O
design	O
or	O
due	O
to	O
shifts	O
in	O
technology	O
.	O
</s>
<s>
Computer	B-General_Concept
architecture	I-General_Concept
is	O
the	O
combination	O
of	O
microarchitecture	B-General_Concept
and	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
The	O
ISA	B-General_Concept
is	O
roughly	O
the	O
same	O
as	O
the	O
programming	O
model	O
of	O
a	O
processor	B-General_Concept
as	O
seen	O
by	O
an	O
assembly	B-Language
language	I-Language
programmer	O
or	O
compiler	O
writer	O
.	O
</s>
<s>
The	O
ISA	B-General_Concept
includes	O
the	O
instructions	O
,	O
execution	B-Device
model	I-Device
,	O
processor	B-General_Concept
registers	I-General_Concept
,	O
address	O
and	O
data	O
formats	O
among	O
other	O
things	O
.	O
</s>
<s>
The	O
microarchitecture	B-General_Concept
includes	O
the	O
constituent	O
parts	O
of	O
the	O
processor	B-General_Concept
and	O
how	O
these	O
interconnect	B-General_Concept
and	O
interoperate	O
to	O
implement	O
the	O
ISA	B-General_Concept
.	O
</s>
<s>
The	O
microarchitecture	B-General_Concept
of	O
a	O
machine	O
is	O
usually	O
represented	O
as	O
(	O
more	O
or	O
less	O
detailed	O
)	O
diagrams	O
that	O
describe	O
the	O
interconnections	O
of	O
the	O
various	O
microarchitectural	B-General_Concept
elements	O
of	O
the	O
machine	O
,	O
which	O
may	O
be	O
anything	O
from	O
single	O
gates	O
and	O
registers	O
,	O
to	O
complete	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
(	O
ALUs	O
)	O
and	O
even	O
larger	O
elements	O
.	O
</s>
<s>
These	O
diagrams	O
generally	O
separate	O
the	O
datapath	B-General_Concept
(	O
where	O
data	O
is	O
placed	O
)	O
and	O
the	O
control	O
path	O
(	O
which	O
can	O
be	O
said	O
to	O
steer	O
the	O
data	O
)	O
.	O
</s>
<s>
The	O
person	O
designing	O
a	O
system	O
usually	O
draws	O
the	O
specific	O
microarchitecture	B-General_Concept
as	O
a	O
kind	O
of	O
data	B-Application
flow	I-Application
diagram	I-Application
.	O
</s>
<s>
Like	O
a	O
block	B-Application
diagram	I-Application
,	O
the	O
microarchitecture	B-General_Concept
diagram	O
shows	O
microarchitectural	B-General_Concept
elements	O
such	O
as	O
the	O
arithmetic	B-General_Concept
and	I-General_Concept
logic	I-General_Concept
unit	I-General_Concept
and	O
the	O
register	B-General_Concept
file	I-General_Concept
as	O
a	O
single	O
schematic	B-Application
symbol	O
.	O
</s>
<s>
Typically	O
,	O
the	O
diagram	O
connects	O
those	O
elements	O
with	O
arrows	O
,	O
thick	O
lines	O
and	O
thin	O
lines	O
to	O
distinguish	O
between	O
three-state	B-Device
buses	O
(	O
which	O
require	O
a	O
three-state	B-Device
buffer	I-Device
for	O
each	O
device	O
that	O
drives	O
the	O
bus	O
)	O
,	O
unidirectional	O
buses	O
(	O
always	O
driven	O
by	O
a	O
single	O
source	O
,	O
such	O
as	O
the	O
way	O
the	O
address	O
bus	O
on	O
simpler	O
computers	O
is	O
always	O
driven	O
by	O
the	O
memory	B-General_Concept
address	I-General_Concept
register	I-General_Concept
)	O
,	O
and	O
individual	O
control	O
lines	O
.	O
</s>
<s>
Very	O
simple	O
computers	O
have	O
a	O
single	O
data	B-General_Concept
bus	I-General_Concept
organization	O
they	O
have	O
a	O
single	O
three-state	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
The	O
diagram	O
of	O
more	O
complex	O
computers	O
usually	O
shows	O
multiple	O
three-state	B-Device
buses	O
,	O
which	O
help	O
the	O
machine	O
do	O
more	O
operations	O
simultaneously	O
.	O
</s>
<s>
Each	O
microarchitectural	B-General_Concept
element	O
is	O
in	O
turn	O
represented	O
by	O
a	O
schematic	B-Application
describing	O
the	O
interconnections	O
of	O
logic	O
gates	O
used	O
to	O
implement	O
it	O
.	O
</s>
<s>
Each	O
logic	O
gate	O
is	O
in	O
turn	O
represented	O
by	O
a	O
circuit	B-Application
diagram	I-Application
describing	O
the	O
connections	O
of	O
the	O
transistors	O
used	O
to	O
implement	O
it	O
in	O
some	O
particular	O
logic	B-General_Concept
family	I-General_Concept
.	O
</s>
<s>
Machines	O
with	O
different	O
microarchitectures	B-General_Concept
may	O
have	O
the	O
same	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
,	O
and	O
thus	O
be	O
capable	O
of	O
executing	O
the	O
same	O
programs	O
.	O
</s>
<s>
New	O
microarchitectures	B-General_Concept
and/or	O
circuitry	O
solutions	O
,	O
along	O
with	O
advances	O
in	O
semiconductor	O
manufacturing	O
,	O
are	O
what	O
allows	O
newer	O
generations	O
of	O
processors	O
to	O
achieve	O
higher	O
performance	O
while	O
using	O
the	O
same	O
ISA	B-General_Concept
.	O
</s>
<s>
In	O
principle	O
,	O
a	O
single	O
microarchitecture	B-General_Concept
could	O
execute	O
several	O
different	O
ISAs	O
with	O
only	O
minor	O
changes	O
to	O
the	O
microcode	B-Device
.	O
</s>
<s>
The	O
pipelined	B-General_Concept
datapath	B-General_Concept
is	O
the	O
most	O
commonly	O
used	O
datapath	B-General_Concept
design	O
in	O
microarchitecture	B-General_Concept
today	O
.	O
</s>
<s>
This	O
technique	O
is	O
used	O
in	O
most	O
modern	O
microprocessors	O
,	O
microcontrollers	B-Architecture
,	O
and	O
DSPs	B-Architecture
.	O
</s>
<s>
The	O
pipelined	B-General_Concept
architecture	O
allows	O
multiple	O
instructions	O
to	O
overlap	O
in	O
execution	O
,	O
much	O
like	O
an	O
assembly	O
line	O
.	O
</s>
<s>
The	O
pipeline	O
includes	O
several	O
different	O
stages	O
which	O
are	O
fundamental	O
in	O
microarchitecture	B-General_Concept
designs	O
.	O
</s>
<s>
The	O
design	O
of	O
pipelines	O
is	O
one	O
of	O
the	O
central	O
microarchitectural	B-General_Concept
tasks	O
.	O
</s>
<s>
Execution	O
units	O
are	O
also	O
essential	O
to	O
microarchitecture	B-General_Concept
.	O
</s>
<s>
Execution	O
units	O
include	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
(	O
ALU	O
)	O
,	O
floating	B-General_Concept
point	I-General_Concept
units	I-General_Concept
(	O
FPU	O
)	O
,	O
load/store	O
units	O
,	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
and	O
SIMD	B-Device
.	O
</s>
<s>
These	O
units	O
perform	O
the	O
operations	O
or	O
calculations	O
of	O
the	O
processor	B-General_Concept
.	O
</s>
<s>
The	O
choice	O
of	O
the	O
number	O
of	O
execution	O
units	O
,	O
their	O
latency	O
and	O
throughput	O
is	O
a	O
central	O
microarchitectural	B-General_Concept
design	O
task	O
.	O
</s>
<s>
The	O
size	O
,	O
latency	O
,	O
throughput	O
and	O
connectivity	O
of	O
memories	O
within	O
the	O
system	O
are	O
also	O
microarchitectural	B-General_Concept
decisions	O
.	O
</s>
<s>
System-level	O
design	O
decisions	O
such	O
as	O
whether	O
or	O
not	O
to	O
include	O
peripherals	O
,	O
such	O
as	O
memory	B-General_Concept
controllers	I-General_Concept
,	O
can	O
be	O
considered	O
part	O
of	O
the	O
microarchitectural	B-General_Concept
design	O
process	O
.	O
</s>
<s>
Unlike	O
architectural	O
design	O
,	O
where	O
achieving	O
a	O
specific	O
performance	O
level	O
is	O
the	O
main	O
goal	O
,	O
microarchitectural	B-General_Concept
design	O
pays	O
closer	O
attention	O
to	O
other	O
constraints	O
.	O
</s>
<s>
Since	O
microarchitecture	B-General_Concept
design	O
decisions	O
directly	O
affect	O
what	O
goes	O
into	O
a	O
system	O
,	O
attention	O
must	O
be	O
paid	O
to	O
issues	O
such	O
as	O
chip	O
area/cost	O
,	O
power	O
consumption	O
,	O
logic	O
complexity	O
,	O
ease	O
of	O
connectivity	O
,	O
manufacturability	O
,	O
ease	O
of	O
debugging	O
,	O
and	O
testability	O
.	O
</s>
<s>
However	O
,	O
other	O
microarchitectures	B-General_Concept
often	O
perform	O
more	O
instructions	O
per	O
unit	O
time	O
,	O
using	O
the	O
same	O
logic	B-General_Concept
family	I-General_Concept
.	O
</s>
<s>
In	O
the	O
control	O
logic	O
,	O
the	O
combination	O
of	O
cycle	O
counter	O
,	O
cycle	O
state	O
(	O
high	O
or	O
low	O
)	O
and	O
the	O
bits	O
of	O
the	O
instruction	O
decode	O
register	B-General_Concept
determine	O
exactly	O
what	O
each	O
part	O
of	O
the	O
computer	O
should	O
be	O
doing	O
.	O
</s>
<s>
If	O
the	O
logic	O
table	O
is	O
placed	O
in	O
a	O
memory	O
and	O
used	O
to	O
actually	O
run	O
a	O
real	O
computer	O
,	O
it	O
is	O
called	O
a	O
microprogram	B-Device
.	I-Device
</s>
<s>
In	O
some	O
computer	B-General_Concept
designs	I-General_Concept
,	O
the	O
logic	O
table	O
is	O
optimized	O
into	O
the	O
form	O
of	O
combinational	O
logic	O
made	O
from	O
logic	O
gates	O
,	O
usually	O
using	O
a	O
computer	O
program	O
that	O
optimizes	O
logic	O
.	O
</s>
<s>
Early	O
computers	O
used	O
ad-hoc	O
logic	O
design	O
for	O
control	O
until	O
Maurice	O
Wilkes	O
invented	O
this	O
tabular	O
approach	O
and	O
called	O
it	O
microprogramming	B-Device
.	O
</s>
<s>
Complicating	O
this	O
simple-looking	O
series	O
of	O
steps	O
is	O
the	O
fact	O
that	O
the	O
memory	B-General_Concept
hierarchy	I-General_Concept
,	O
which	O
includes	O
caching	B-General_Concept
,	O
main	O
memory	O
and	O
non-volatile	O
storage	O
like	O
hard	B-Device
disks	I-Device
(	O
where	O
the	O
program	O
instructions	O
and	O
data	O
reside	O
)	O
,	O
has	O
always	O
been	O
slower	O
than	O
the	O
processor	B-General_Concept
itself	O
.	O
</s>
<s>
Step	O
(	O
2	O
)	O
often	O
introduces	O
a	O
lengthy	O
(	O
in	O
CPU	O
terms	O
)	O
delay	O
while	O
the	O
data	O
arrives	O
over	O
the	O
computer	B-General_Concept
bus	I-General_Concept
.	O
</s>
<s>
Initially	O
,	O
these	O
techniques	O
could	O
only	O
be	O
implemented	O
on	O
expensive	O
mainframes	B-Architecture
or	O
supercomputers	B-Architecture
due	O
to	O
the	O
amount	O
of	O
circuitry	O
needed	O
for	O
these	O
techniques	O
.	O
</s>
<s>
Instruction	B-General_Concept
sets	I-General_Concept
have	O
shifted	O
over	O
the	O
years	O
,	O
from	O
originally	O
very	O
simple	O
to	O
sometimes	O
very	O
complex	O
(	O
in	O
various	O
respects	O
)	O
.	O
</s>
<s>
In	O
recent	O
years	O
,	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
architectures	I-Architecture
,	O
VLIW	B-General_Concept
and	O
EPIC	B-General_Concept
types	O
have	O
been	O
in	O
fashion	O
.	O
</s>
<s>
Architectures	O
that	O
are	O
dealing	O
with	O
data	B-Operating_System
parallelism	I-Operating_System
include	O
SIMD	B-Device
and	O
Vectors	B-Operating_System
.	O
</s>
<s>
Some	O
labels	O
used	O
to	O
denote	O
classes	O
of	O
CPU	B-General_Concept
architectures	I-General_Concept
are	O
not	O
particularly	O
descriptive	O
,	O
especially	O
so	O
the	O
CISC	B-Architecture
label	O
;	O
many	O
early	O
designs	O
retroactively	O
denoted	O
"	O
CISC	B-Architecture
"	O
are	O
in	O
fact	O
significantly	O
simpler	O
than	O
modern	O
RISC	O
processors	O
(	O
in	O
several	O
respects	O
)	O
.	O
</s>
<s>
However	O
,	O
the	O
choice	O
of	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
may	O
greatly	O
affect	O
the	O
complexity	O
of	O
implementing	O
high-performance	O
devices	O
.	O
</s>
<s>
Such	O
uniform	O
instructions	O
were	O
easily	O
fetched	O
,	O
decoded	O
and	O
executed	O
in	O
a	O
pipelined	B-General_Concept
fashion	O
and	O
a	O
simple	O
strategy	O
to	O
reduce	O
the	O
number	O
of	O
logic	O
levels	O
in	O
order	O
to	O
reach	O
high	O
operating	O
frequencies	O
;	O
instruction	O
cache-memories	B-General_Concept
compensated	O
for	O
the	O
higher	O
operating	O
frequency	O
and	O
inherently	O
low	O
code	O
density	O
while	O
large	O
register	B-General_Concept
sets	O
were	O
used	O
to	O
factor	O
out	O
as	O
much	O
of	O
the	O
(	O
slow	O
)	O
memory	O
accesses	O
as	O
possible	O
.	O
</s>
<s>
One	O
of	O
the	O
first	O
,	O
and	O
most	O
powerful	O
,	O
techniques	O
to	O
improve	O
performance	O
is	O
the	O
use	O
of	O
instruction	B-General_Concept
pipelining	I-General_Concept
.	O
</s>
<s>
Early	O
processor	B-General_Concept
designs	I-General_Concept
would	O
carry	O
out	O
all	O
of	O
the	O
steps	O
above	O
for	O
one	O
instruction	O
before	O
moving	O
onto	O
the	O
next	O
.	O
</s>
<s>
Pipelining	O
improves	O
performance	O
by	O
allowing	O
a	O
number	O
of	O
instructions	O
to	O
work	O
their	O
way	O
through	O
the	O
processor	B-General_Concept
at	O
the	O
same	O
time	O
.	O
</s>
<s>
In	O
the	O
same	O
basic	O
example	O
,	O
the	O
processor	B-General_Concept
would	O
start	O
to	O
decode	O
(	O
step	O
1	O
)	O
a	O
new	O
instruction	O
while	O
the	O
last	O
one	O
was	O
waiting	O
for	O
results	O
.	O
</s>
<s>
This	O
would	O
allow	O
up	O
to	O
four	O
instructions	O
to	O
be	O
"	O
in	O
flight	O
"	O
at	O
one	O
time	O
,	O
making	O
the	O
processor	B-General_Concept
look	O
four	O
times	O
as	O
fast	O
.	O
</s>
<s>
The	O
processor	B-General_Concept
as	O
a	O
whole	O
operates	O
in	O
an	O
assembly	O
line	O
fashion	O
,	O
with	O
instructions	O
coming	O
in	O
one	O
side	O
and	O
results	O
out	O
the	O
other	O
.	O
</s>
<s>
Due	O
to	O
the	O
reduced	O
complexity	O
of	O
the	O
classic	B-General_Concept
RISC	I-General_Concept
pipeline	I-General_Concept
,	O
the	O
pipelined	B-General_Concept
core	O
and	O
an	O
instruction	O
cache	B-General_Concept
could	O
be	O
placed	O
on	O
the	O
same	O
size	O
die	O
that	O
would	O
otherwise	O
fit	O
the	O
core	O
alone	O
on	O
a	O
CISC	B-Architecture
design	O
.	O
</s>
<s>
Early	O
designs	O
like	O
the	O
SPARC	B-Architecture
and	O
MIPS	B-Device
often	O
ran	O
over	O
10	O
times	O
as	O
fast	O
as	O
Intel	O
and	O
Motorola	O
CISC	B-Architecture
solutions	O
at	O
the	O
same	O
clock	O
speed	O
and	O
price	O
.	O
</s>
<s>
By	O
1986	O
the	O
top-of-the-line	O
VAX	O
implementation	O
(	O
VAX	B-Device
8800	I-Device
)	O
was	O
a	O
heavily	O
pipelined	B-General_Concept
design	O
,	O
slightly	O
predating	O
the	O
first	O
commercial	O
MIPS	B-Device
and	O
SPARC	B-Architecture
designs	O
.	O
</s>
<s>
Most	O
modern	O
CPUs	O
(	O
even	O
embedded	O
CPUs	O
)	O
are	O
now	O
pipelined	B-General_Concept
,	O
and	O
microcoded	B-Device
CPUs	O
with	O
no	O
pipelining	O
are	O
seen	O
only	O
in	O
the	O
most	O
area-constrained	O
embedded	O
processors	O
.	O
</s>
<s>
Large	O
CISC	B-Architecture
machines	O
,	O
from	O
the	O
VAX	B-Device
8800	I-Device
to	O
the	O
modern	O
Pentium	O
4	O
and	O
Athlon	O
,	O
are	O
implemented	O
with	O
both	O
microcode	B-Device
and	O
pipelines	O
.	O
</s>
<s>
Improvements	O
in	O
pipelining	O
and	O
caching	B-General_Concept
are	O
the	O
two	O
major	O
microarchitectural	B-General_Concept
advances	O
that	O
have	O
enabled	O
processor	B-General_Concept
performance	O
to	O
keep	O
pace	O
with	O
the	O
circuit	O
technology	O
on	O
which	O
they	O
are	O
based	O
.	O
</s>
<s>
One	O
of	O
the	O
most	O
common	O
was	O
to	O
add	O
an	O
ever-increasing	O
amount	O
of	O
cache	B-General_Concept
memory	I-General_Concept
on-die	O
.	O
</s>
<s>
Cache	B-General_Concept
is	O
very	O
fast	O
and	O
expensive	O
memory	O
.	O
</s>
<s>
The	O
CPU	O
includes	O
a	O
cache	B-General_Concept
controller	O
which	O
automates	O
reading	O
and	O
writing	O
from	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
If	O
the	O
data	O
is	O
already	O
in	O
the	O
cache	B-General_Concept
it	O
is	O
accessed	O
from	O
there	O
–	O
at	O
considerable	O
time	O
savings	O
,	O
whereas	O
if	O
it	O
is	O
not	O
the	O
processor	B-General_Concept
is	O
"	O
stalled	O
"	O
while	O
the	O
cache	B-General_Concept
controller	O
reads	O
it	O
in	O
.	O
</s>
<s>
RISC	O
designs	O
started	O
adding	O
cache	B-General_Concept
in	O
the	O
mid-to-late	O
1980s	O
,	O
often	O
only	O
4KB	O
in	O
total	O
.	O
</s>
<s>
This	O
number	O
grew	O
over	O
time	O
,	O
and	O
typical	O
CPUs	O
now	O
have	O
at	O
least	O
2	O
MB	O
,	O
while	O
more	O
powerful	O
CPUs	O
come	O
with	O
4	O
or	O
6	O
or	O
12MB	O
or	O
even	O
32MB	O
or	O
more	O
,	O
with	O
the	O
most	O
being	O
768MB	O
in	O
the	O
newly	O
released	O
EPYC	O
Milan-X	O
line	O
,	O
organized	O
in	O
multiple	O
levels	O
of	O
a	O
memory	B-General_Concept
hierarchy	I-General_Concept
.	O
</s>
<s>
Generally	O
speaking	O
,	O
more	O
cache	B-General_Concept
means	O
more	O
performance	O
,	O
due	O
to	O
reduced	O
stalling	O
.	O
</s>
<s>
Caches	B-General_Concept
and	O
pipelines	O
were	O
a	O
perfect	O
match	O
for	O
each	O
other	O
.	O
</s>
<s>
Using	O
on-chip	B-General_Concept
cache	I-General_Concept
memory	O
instead	O
,	O
meant	O
that	O
a	O
pipeline	O
could	O
run	O
at	O
the	O
speed	O
of	O
the	O
cache	B-General_Concept
access	O
latency	O
,	O
a	O
much	O
smaller	O
length	O
of	O
time	O
.	O
</s>
<s>
One	O
barrier	O
to	O
achieving	O
higher	O
performance	O
through	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
stems	O
from	O
pipeline	O
stalls	O
and	O
flushes	O
due	O
to	O
branches	O
.	O
</s>
<s>
Normally	O
,	O
whether	O
a	O
conditional	O
branch	O
will	O
be	O
taken	O
is	O
n't	O
known	O
until	O
late	O
in	O
the	O
pipeline	O
as	O
conditional	O
branches	O
depend	O
on	O
results	O
coming	O
from	O
a	O
register	B-General_Concept
.	O
</s>
<s>
From	O
the	O
time	O
that	O
the	O
processor	B-General_Concept
's	O
instruction	O
decoder	O
has	O
figured	O
out	O
that	O
it	O
has	O
encountered	O
a	O
conditional	O
branch	O
instruction	O
to	O
the	O
time	O
that	O
the	O
deciding	O
register	B-General_Concept
value	O
can	O
be	O
read	O
out	O
,	O
the	O
pipeline	O
needs	O
to	O
be	O
stalled	O
for	O
several	O
cycles	O
,	O
or	O
if	O
it	O
's	O
not	O
and	O
the	O
branch	O
is	O
taken	O
,	O
the	O
pipeline	O
needs	O
to	O
be	O
flushed	O
.	O
</s>
<s>
Techniques	O
such	O
as	O
branch	B-General_Concept
prediction	I-General_Concept
and	O
speculative	B-General_Concept
execution	I-General_Concept
are	O
used	O
to	O
lessen	O
these	O
branch	O
penalties	O
.	O
</s>
<s>
Branch	B-General_Concept
prediction	I-General_Concept
is	O
where	O
the	O
hardware	O
makes	O
educated	O
guesses	O
on	O
whether	O
a	O
particular	O
branch	O
will	O
be	O
taken	O
.	O
</s>
<s>
The	O
guess	O
allows	O
the	O
hardware	O
to	O
prefetch	O
instructions	O
without	O
waiting	O
for	O
the	O
register	B-General_Concept
read	O
.	O
</s>
<s>
Speculative	B-General_Concept
execution	I-General_Concept
is	O
a	O
further	O
enhancement	O
in	O
which	O
the	O
code	O
along	O
the	O
predicted	O
path	O
is	O
not	O
just	O
prefetched	O
but	O
also	O
executed	O
before	O
it	O
is	O
known	O
whether	O
the	O
branch	O
should	O
be	O
taken	O
or	O
not	O
.	O
</s>
<s>
In	O
the	O
outline	O
above	O
the	O
processor	B-General_Concept
processes	O
parts	O
of	O
a	O
single	O
instruction	O
at	O
a	O
time	O
.	O
</s>
<s>
This	O
is	O
what	O
superscalar	B-General_Concept
processors	I-General_Concept
achieve	O
,	O
by	O
replicating	O
functional	O
units	O
such	O
as	O
ALUs	O
.	O
</s>
<s>
The	O
replication	O
of	O
functional	O
units	O
was	O
only	O
made	O
possible	O
when	O
the	O
die	O
area	O
of	O
a	O
single-issue	O
processor	B-General_Concept
no	O
longer	O
stretched	O
the	O
limits	O
of	O
what	O
could	O
be	O
reliably	O
manufactured	O
.	O
</s>
<s>
By	O
the	O
late	O
1980s	O
,	O
superscalar	B-General_Concept
designs	O
started	O
to	O
enter	O
the	O
market	O
place	O
.	O
</s>
<s>
In	O
modern	O
designs	O
it	O
is	O
common	O
to	O
find	O
two	O
load	O
units	O
,	O
one	O
store	O
(	O
many	O
instructions	O
have	O
no	O
results	O
to	O
store	O
)	O
,	O
two	O
or	O
more	O
integer	O
math	O
units	O
,	O
two	O
or	O
more	O
floating	B-General_Concept
point	I-General_Concept
units	I-General_Concept
,	O
and	O
often	O
a	O
SIMD	B-Device
unit	O
of	O
some	O
sort	O
.	O
</s>
<s>
The	O
addition	O
of	O
caches	B-General_Concept
reduces	O
the	O
frequency	O
or	O
duration	O
of	O
stalls	O
due	O
to	O
waiting	O
for	O
data	O
to	O
be	O
fetched	O
from	O
the	O
memory	B-General_Concept
hierarchy	I-General_Concept
,	O
but	O
does	O
not	O
get	O
rid	O
of	O
these	O
stalls	O
entirely	O
.	O
</s>
<s>
In	O
early	O
designs	O
a	O
cache	B-General_Concept
miss	O
would	O
force	O
the	O
cache	B-General_Concept
controller	O
to	O
stall	O
the	O
processor	B-General_Concept
and	O
wait	O
.	O
</s>
<s>
Of	O
course	O
there	O
may	O
be	O
some	O
other	O
instruction	O
in	O
the	O
program	O
whose	O
data	O
is	O
available	O
in	O
the	O
cache	B-General_Concept
at	O
that	O
point	O
.	O
</s>
<s>
Out-of-order	B-General_Concept
execution	I-General_Concept
allows	O
that	O
ready	O
instruction	O
to	O
be	O
processed	O
while	O
an	O
older	O
instruction	O
waits	O
on	O
the	O
cache	B-General_Concept
,	O
then	O
re-orders	O
the	O
results	O
to	O
make	O
it	O
appear	O
that	O
everything	O
happened	O
in	O
the	O
programmed	O
order	O
.	O
</s>
<s>
Register	B-General_Concept
renaming	O
refers	O
to	O
a	O
technique	O
used	O
to	O
avoid	O
unnecessary	O
serialized	O
execution	O
of	O
program	O
instructions	O
because	O
of	O
the	O
reuse	O
of	O
the	O
same	O
registers	O
by	O
those	O
instructions	O
.	O
</s>
<s>
Suppose	O
we	O
have	O
two	O
groups	O
of	O
instruction	O
that	O
will	O
use	O
the	O
same	O
register	B-General_Concept
.	O
</s>
<s>
One	O
set	O
of	O
instructions	O
is	O
executed	O
first	O
to	O
leave	O
the	O
register	B-General_Concept
to	O
the	O
other	O
set	O
,	O
but	O
if	O
the	O
other	O
set	O
is	O
assigned	O
to	O
a	O
different	O
similar	O
register	B-General_Concept
,	O
both	O
sets	O
of	O
instructions	O
can	O
be	O
executed	O
in	O
parallel	O
(	O
or	O
)	O
in	O
series	O
.	O
</s>
<s>
Computer	B-General_Concept
architects	I-General_Concept
have	O
become	O
stymied	O
by	O
the	O
growing	O
mismatch	O
in	O
CPU	O
operating	O
frequencies	O
and	O
DRAM	O
access	O
times	O
.	O
</s>
<s>
None	O
of	O
the	O
techniques	O
that	O
exploited	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
(	O
ILP	O
)	O
within	O
one	O
program	O
could	O
make	O
up	O
for	O
the	O
long	O
stalls	O
that	O
occurred	O
when	O
data	O
had	O
to	O
be	O
fetched	O
from	O
main	O
memory	O
.	O
</s>
<s>
For	O
these	O
reasons	O
,	O
newer	O
generations	O
of	O
computers	O
have	O
started	O
to	O
exploit	O
higher	O
levels	O
of	O
parallelism	O
that	O
exist	O
outside	O
of	O
a	O
single	O
program	O
or	O
program	B-Operating_System
thread	I-Operating_System
.	O
</s>
<s>
This	O
idea	O
originated	O
in	O
the	O
mainframe	B-Architecture
market	O
where	O
online	B-General_Concept
transaction	I-General_Concept
processing	I-General_Concept
emphasized	O
not	O
just	O
the	O
execution	O
speed	O
of	O
one	O
transaction	O
,	O
but	O
the	O
capacity	O
to	O
deal	O
with	O
massive	O
numbers	O
of	O
transactions	O
.	O
</s>
<s>
One	O
technique	O
of	O
how	O
this	O
parallelism	O
is	O
achieved	O
is	O
through	O
multiprocessing	B-Operating_System
systems	O
,	O
computer	O
systems	O
with	O
multiple	O
CPUs	O
.	O
</s>
<s>
Once	O
reserved	O
for	O
high-end	O
mainframes	B-Architecture
and	O
supercomputers	B-Architecture
,	O
small-scale	O
(	O
2	O
–	O
8	O
)	O
multiprocessors	B-Operating_System
servers	O
have	O
become	O
commonplace	O
for	O
the	O
small	O
business	O
market	O
.	O
</s>
<s>
For	O
large	O
corporations	O
,	O
large	O
scale	O
(	O
16	O
–	O
256	O
)	O
multiprocessors	B-Operating_System
are	O
common	O
.	O
</s>
<s>
Even	O
personal	B-Device
computers	I-Device
with	O
multiple	O
CPUs	O
have	O
appeared	O
since	O
the	O
1990s	O
.	O
</s>
<s>
With	O
further	O
transistor	O
size	O
reductions	O
made	O
available	O
with	O
semiconductor	O
technology	O
advances	O
,	O
multi-core	B-Architecture
CPUs	I-Architecture
have	O
appeared	O
where	O
multiple	O
CPUs	O
are	O
implemented	O
on	O
the	O
same	O
silicon	O
chip	O
.	O
</s>
<s>
Some	O
designs	O
,	O
such	O
as	O
Sun	O
Microsystems	O
 '	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
have	O
reverted	O
to	O
simpler	O
(	O
scalar	O
,	O
in-order	O
)	O
designs	O
in	O
order	O
to	O
fit	O
more	O
processors	O
on	O
one	O
piece	O
of	O
silicon	O
.	O
</s>
<s>
Another	O
technique	O
that	O
has	O
become	O
more	O
popular	O
recently	O
is	O
multithreading	B-General_Concept
.	O
</s>
<s>
In	O
multithreading	B-General_Concept
,	O
when	O
the	O
processor	B-General_Concept
has	O
to	O
fetch	O
data	O
from	O
slow	O
system	O
memory	O
,	O
instead	O
of	O
stalling	O
for	O
the	O
data	O
to	O
arrive	O
,	O
the	O
processor	B-General_Concept
switches	O
to	O
another	O
program	O
or	O
program	B-Operating_System
thread	I-Operating_System
which	O
is	O
ready	O
to	O
execute	O
.	O
</s>
<s>
Though	O
this	O
does	O
not	O
speed	O
up	O
a	O
particular	O
program/thread	O
,	O
it	O
increases	O
the	O
overall	O
system	O
throughput	O
by	O
reducing	O
the	O
time	O
the	O
CPU	O
is	O
idle	O
.	O
</s>
<s>
Conceptually	O
,	O
multithreading	B-General_Concept
is	O
equivalent	O
to	O
a	O
context	B-Operating_System
switch	I-Operating_System
at	O
the	O
operating	O
system	O
level	O
.	O
</s>
<s>
The	O
difference	O
is	O
that	O
a	O
multithreaded	B-Operating_System
CPU	I-Operating_System
can	O
do	O
a	O
thread	B-Operating_System
switch	I-Operating_System
in	O
one	O
CPU	O
cycle	O
instead	O
of	O
the	O
hundreds	O
or	O
thousands	O
of	O
CPU	O
cycles	O
a	O
context	B-Operating_System
switch	I-Operating_System
normally	O
requires	O
.	O
</s>
<s>
This	O
is	O
achieved	O
by	O
replicating	O
the	O
state	O
hardware	O
(	O
such	O
as	O
the	O
register	B-General_Concept
file	I-General_Concept
and	O
program	B-General_Concept
counter	I-General_Concept
)	O
for	O
each	O
active	O
thread	B-Operating_System
.	O
</s>
<s>
A	O
further	O
enhancement	O
is	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
.	O
</s>
<s>
This	O
technique	O
allows	O
superscalar	B-General_Concept
CPUs	O
to	O
execute	O
instructions	O
from	O
different	O
programs/threads	O
simultaneously	O
in	O
the	O
same	O
cycle	O
.	O
</s>
