<s>
In	O
computer	O
central	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
,	O
micro-operations	B-General_Concept
(	O
also	O
known	O
as	O
micro-ops	B-General_Concept
or	O
μops	B-General_Concept
,	O
historically	O
also	O
as	O
micro-actions	B-General_Concept
)	O
are	O
detailed	O
low-level	O
instructions	O
used	O
in	O
some	O
designs	O
to	O
implement	O
complex	O
machine	O
instructions	O
(	O
sometimes	O
termed	O
macro-instructions	O
in	O
this	O
context	O
)	O
.	O
</s>
<s>
Usually	O
,	O
micro-operations	B-General_Concept
perform	O
basic	O
operations	O
on	O
data	O
stored	O
in	O
one	O
or	O
more	O
registers	B-General_Concept
,	O
including	O
transferring	O
data	O
between	O
registers	B-General_Concept
or	O
between	O
registers	B-General_Concept
and	O
external	O
buses	B-General_Concept
of	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
,	O
and	O
performing	O
arithmetic	O
or	O
logical	O
operations	O
on	O
registers	B-General_Concept
.	O
</s>
<s>
In	O
a	O
typical	O
fetch-decode-execute	B-General_Concept
cycle	I-General_Concept
,	O
each	O
step	O
of	O
a	O
macro-instruction	O
is	O
decomposed	O
during	O
its	O
execution	O
so	O
the	O
CPU	O
determines	O
and	O
steps	O
through	O
a	O
series	O
of	O
micro-operations	B-General_Concept
.	O
</s>
<s>
The	O
execution	O
of	O
micro-operations	B-General_Concept
is	O
performed	O
under	O
control	O
of	O
the	O
CPU	O
's	O
control	B-General_Concept
unit	I-General_Concept
,	O
which	O
decides	O
on	O
their	O
execution	O
while	O
performing	O
various	O
optimizations	O
such	O
as	O
reordering	O
,	O
fusion	O
and	O
caching	O
.	O
</s>
<s>
Various	O
forms	O
of	O
μops	B-General_Concept
have	O
long	O
been	O
the	O
basis	O
for	O
traditional	O
microcode	B-Device
routines	O
used	O
to	O
simplify	O
the	O
implementation	O
of	O
a	O
particular	O
CPU	B-General_Concept
design	I-General_Concept
or	O
perhaps	O
just	O
the	O
sequencing	O
of	O
certain	O
multi-step	O
operations	O
or	O
addressing	O
modes	O
.	O
</s>
<s>
More	O
recently	O
,	O
μops	B-General_Concept
have	O
also	O
been	O
employed	O
in	O
a	O
different	O
way	O
in	O
order	O
to	O
let	O
modern	O
CISC	B-Architecture
processors	I-Architecture
more	O
easily	O
handle	O
asynchronous	O
parallel	O
and	O
speculative	O
execution	O
:	O
As	O
with	O
traditional	O
microcode	B-Device
,	O
one	O
or	O
more	O
table	O
lookups	O
(	O
or	O
equivalent	O
)	O
is	O
done	O
to	O
locate	O
the	O
appropriate	O
μop-sequence	O
based	O
on	O
the	O
encoding	O
and	O
semantics	O
of	O
the	O
machine	O
instruction	O
(	O
the	O
decoding	O
or	O
translation	O
step	O
)	O
,	O
however	O
,	O
instead	O
of	O
having	O
rigid	O
μop-sequences	O
controlling	O
the	O
CPU	O
directly	O
from	O
a	O
microcode-ROM	O
,	O
μops	B-General_Concept
are	O
here	O
dynamically	O
buffered	O
for	O
rescheduling	O
before	O
being	O
executed	O
.	O
</s>
<s>
This	O
buffering	O
means	O
that	O
the	O
fetch	O
and	O
decode	O
stages	O
can	O
be	O
more	O
detached	O
from	O
the	O
execution	O
units	O
than	O
is	O
feasible	O
in	O
a	O
more	O
traditional	O
microcoded	B-Device
(	O
or	O
hard-wired	O
)	O
design	O
.	O
</s>
<s>
As	O
this	O
allows	O
a	O
degree	O
of	O
freedom	O
regarding	O
execution	O
order	O
,	O
it	O
makes	O
some	O
extraction	O
of	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
out	O
of	O
a	O
normal	O
single-threaded	O
program	O
possible	O
(	O
provided	O
that	O
dependencies	O
are	O
checked	O
etc	O
.	O
)	O
.	O
</s>
<s>
It	O
opens	O
up	O
for	O
more	O
analysis	O
and	O
therefore	O
also	O
for	O
reordering	O
of	O
code	O
sequences	O
in	O
order	O
to	O
dynamically	O
optimize	O
mapping	O
and	O
scheduling	O
of	O
μops	B-General_Concept
onto	O
machine	O
resources	O
(	O
such	O
as	O
ALUs	B-General_Concept
,	O
load/store	O
units	O
etc	O
.	O
)	O
.	O
</s>
<s>
As	O
this	O
happens	O
on	O
the	O
μop-level	O
,	O
sub-operations	O
of	O
different	O
machine	O
(	O
macro	O
)	O
instructions	O
may	O
often	O
intermix	O
in	O
a	O
particular	O
μop-sequence	O
,	O
forming	O
partially	O
reordered	O
machine	O
instructions	O
as	O
a	O
direct	O
consequence	O
of	O
the	O
out-of-order	O
dispatching	O
of	O
microinstructions	B-Device
from	O
several	O
macro	O
instructions	O
.	O
</s>
<s>
However	O
,	O
this	O
is	O
not	O
the	O
same	O
as	O
the	O
micro-op	B-General_Concept
fusion	O
,	O
which	O
aims	O
at	O
the	O
fact	O
that	O
a	O
more	O
complex	O
microinstruction	B-Device
may	O
replace	O
a	O
few	O
simpler	O
microinstructions	B-Device
in	O
certain	O
cases	O
,	O
typically	O
in	O
order	O
to	O
minimize	O
state	O
changes	O
and	O
usage	O
of	O
the	O
queue	O
and	O
re-order	B-General_Concept
buffer	I-General_Concept
space	O
,	O
therefore	O
reducing	O
power	O
consumption	O
.	O
</s>
<s>
Micro-op	B-General_Concept
fusion	O
is	O
used	O
in	O
some	O
modern	O
CPU	B-General_Concept
designs	I-General_Concept
.	O
</s>
<s>
Execution	O
optimization	O
has	O
gone	O
even	O
further	O
;	O
processors	O
not	O
only	O
translate	O
many	O
machine	O
instructions	O
into	O
a	O
series	O
of	O
μops	B-General_Concept
,	O
but	O
also	O
do	O
the	O
opposite	O
when	O
appropriate	O
;	O
they	O
combine	O
certain	O
machine	O
instruction	O
sequences	O
(	O
such	O
as	O
a	O
compare	O
followed	O
by	O
a	O
conditional	O
jump	O
)	O
into	O
a	O
more	O
complex	O
μop	B-General_Concept
which	O
fits	O
the	O
execution	O
model	O
better	O
and	O
thus	O
can	O
be	O
executed	O
faster	O
or	O
with	O
less	O
machine	O
resources	O
involved	O
.	O
</s>
<s>
Another	O
way	O
to	O
try	O
to	O
improve	O
performance	O
is	O
to	O
cache	O
the	O
decoded	O
micro-operations	B-General_Concept
in	O
a	O
micro-operation	B-General_Concept
cache	O
,	O
so	O
that	O
if	O
the	O
same	O
macroinstruction	O
is	O
executed	O
again	O
,	O
the	O
processor	O
can	O
directly	O
access	O
the	O
decoded	O
micro-operations	B-General_Concept
from	O
the	O
cache	O
,	O
instead	O
of	O
decoding	O
them	O
again	O
.	O
</s>
<s>
The	O
execution	O
trace	O
cache	O
found	O
in	O
Intel	B-Device
NetBurst	I-Device
microarchitecture	O
(	O
Pentium	B-General_Concept
4	I-General_Concept
)	O
is	O
a	O
widespread	O
example	O
of	O
this	O
technique	O
.	O
</s>
<s>
The	O
size	O
of	O
this	O
cache	O
may	O
be	O
stated	O
in	O
terms	O
of	O
how	O
many	O
thousands	O
(	O
or	O
strictly	O
multiple	O
of	O
1024	O
)	O
of	O
micro-operations	B-General_Concept
it	O
can	O
store	O
:	O
Kμops	B-General_Concept
.	O
</s>
