<s>
Memory	B-General_Concept
type	I-General_Concept
range	I-General_Concept
registers	I-General_Concept
(	O
MTRRs	O
)	O
are	O
a	O
set	O
of	O
processor	B-General_Concept
supplementary	I-General_Concept
capability	I-General_Concept
control	B-Operating_System
registers	I-Operating_System
that	O
provide	O
system	B-Application
software	I-Application
with	O
control	O
of	O
how	O
accesses	O
to	O
memory	B-General_Concept
ranges	O
by	O
the	O
CPU	B-Device
are	O
cached	B-General_Concept
.	O
</s>
<s>
It	O
uses	O
a	O
set	O
of	O
programmable	O
model-specific	B-General_Concept
registers	I-General_Concept
(	O
MSRs	O
)	O
which	O
are	O
special	O
registers	O
provided	O
by	O
most	O
modern	O
CPUs	B-Device
.	O
</s>
<s>
Possible	O
access	O
modes	O
to	O
memory	B-General_Concept
ranges	O
can	O
be	O
uncached	O
,	O
write-through	O
,	O
write-combining	B-Architecture
,	O
write-protect	O
,	O
and	O
write-back	O
.	O
</s>
<s>
In	O
write-back	O
mode	O
,	O
writes	O
are	O
written	O
to	O
the	O
CPU	B-Device
's	O
cache	B-General_Concept
and	O
the	O
cache	B-General_Concept
is	O
marked	O
dirty	O
,	O
so	O
that	O
its	O
contents	O
are	O
written	O
to	O
memory	B-General_Concept
later	O
.	O
</s>
<s>
Write-combining	B-Architecture
allows	O
bus	B-General_Concept
write	O
transfers	O
to	O
be	O
combined	O
into	O
a	O
larger	O
transfer	O
before	O
bursting	B-Architecture
them	O
over	O
the	O
bus	B-General_Concept
to	O
allow	O
more	O
efficient	O
writes	O
to	O
system	O
resources	O
like	O
graphics	B-Device
card	I-Device
memory	B-General_Concept
.	O
</s>
<s>
This	O
often	O
increases	O
the	O
speed	O
of	O
image	O
write	O
operations	O
by	O
several	O
times	O
,	O
at	O
the	O
cost	O
of	O
losing	O
the	O
simple	O
sequential	O
read/write	O
semantics	O
of	O
normal	O
memory	B-General_Concept
.	O
</s>
<s>
Additional	O
bits	O
which	O
are	O
provided	O
on	O
some	O
computer	B-General_Concept
architectures	I-General_Concept
,	O
such	O
as	O
AMD64	B-Device
,	O
allow	O
the	O
shadowing	O
of	O
ROM	B-Device
contents	O
in	O
system	O
memory	B-General_Concept
(	O
shadow	O
ROM	B-Device
)	O
,	O
and	O
the	O
configuration	O
of	O
memory-mapped	B-Architecture
I/O	I-Architecture
.	O
</s>
<s>
In	O
early	O
x86	B-Operating_System
architecture	I-Operating_System
systems	O
,	O
especially	O
where	O
the	O
cache	B-General_Concept
was	O
provided	O
by	O
separate	O
chips	O
outside	O
of	O
the	O
CPU	B-Device
package	O
,	O
this	O
function	O
was	O
controlled	O
by	O
the	O
chipset	B-Device
and	O
configured	O
through	O
BIOS	B-Operating_System
settings	I-Operating_System
.	O
</s>
<s>
When	O
the	O
CPU	B-General_Concept
cache	I-General_Concept
was	O
moved	O
inside	O
the	O
CPU	B-Device
,	O
the	O
CPUs	B-Device
implemented	O
fixed-range	O
MTRRs	O
which	O
cover	O
the	O
first	O
megabyte	O
of	O
memory	B-General_Concept
to	O
be	O
compatible	O
to	O
what	O
PC-BIOSes	O
provided	O
at	O
that	O
time	O
.	O
</s>
<s>
These	O
are	O
used	O
to	O
control	O
the	O
cache	B-General_Concept
policy	O
needed	O
for	O
VGA	B-Protocol
accesses	O
and	O
all	O
other	O
memory-accesses	O
done	O
while	O
the	O
system	O
is	O
in	O
real	B-Application
mode	I-Application
.	O
</s>
<s>
Above	O
1MB	O
,	O
CPUs	B-Device
provide	O
a	O
number	O
of	O
variable-range	O
MTRRs	O
,	O
which	O
can	O
be	O
freely	O
placed	O
and	O
even	O
overlap	O
.	O
</s>
<s>
These	O
variable-range	O
MTRRs	O
can	O
be	O
used	O
to	O
set	O
the	O
caching	O
policy	O
of	O
graphics	O
memory	B-General_Concept
and	O
other	O
memory	B-General_Concept
ranges	O
used	O
by	O
PCI	B-Protocol
devices	O
.	O
</s>
<s>
Starting	O
with	O
the	O
Intel	B-Device
P6	I-Device
family	O
of	O
processors	O
(	O
Pentium	B-Device
Pro	I-Device
,	O
Pentium	B-General_Concept
II	I-General_Concept
and	O
later	O
)	O
,	O
MTRRs	O
may	O
be	O
used	O
to	O
control	O
the	O
processor	O
access	O
to	O
memory	B-General_Concept
ranges	O
.	O
</s>
<s>
The	O
Cyrix	B-General_Concept
6x86	I-General_Concept
,	O
6x86MX	B-General_Concept
and	O
MII	O
processors	O
have	O
Address	B-General_Concept
Range	I-General_Concept
Registers	I-General_Concept
(	O
ARRs	O
)	O
which	O
provide	O
a	O
similar	O
functionality	O
to	O
MTRRs	O
.	O
</s>
<s>
The	O
AMD	O
K6-2	O
(	O
stepping	O
8	O
and	O
above	O
)	O
and	O
K6-III	B-Architecture
processors	O
have	O
two	O
MTRRs	O
.	O
</s>
<s>
The	O
AMD	B-Architecture
Athlon	I-Architecture
family	O
provide	O
8	O
Intel-style	O
MTRRs	O
.	O
</s>
<s>
The	O
Centaur	O
C6	O
WinChip	B-Device
has	O
8	O
MCRs	O
,	O
allowing	O
write-combining	B-Architecture
.	O
</s>
<s>
The	O
VIA	O
Cyrix	B-Device
III	I-Device
and	O
VIA	B-Device
C3	I-Device
CPUs	B-Device
offer	O
8	O
Intel-style	O
MTRRs	O
.	O
</s>
<s>
The	O
memory	B-General_Concept
interface	O
of	O
AMD	O
K8	O
CPUs	B-Device
supports	O
"	O
Extended	O
fixed-range	O
MTRR	O
Type-Field	O
Encodings	O
"	O
which	O
allows	O
one	O
to	O
specify	O
whether	O
accesses	O
to	O
certain	O
address	O
ranges	O
are	O
executed	O
by	O
accessing	O
RAM	B-Architecture
through	O
the	O
Direct	O
Connect	O
Architecture	O
or	O
by	O
executing	O
memory-mapped	B-Architecture
I/O	I-Architecture
.	O
</s>
<s>
This	O
allows	O
,	O
for	O
example	O
,	O
shadow	O
RAM	B-Architecture
to	O
be	O
implemented	O
by	O
copying	O
ROM	B-Device
contents	O
into	O
RAM	B-Architecture
.	O
</s>
<s>
Newer	O
x86	B-Operating_System
CPUs	B-Device
support	O
a	O
more	O
advanced	O
technique	O
called	O
page	B-General_Concept
attribute	I-General_Concept
tables	I-General_Concept
(	O
PATs	O
)	O
that	O
allow	O
for	O
per-page	O
setting	O
of	O
these	O
modes	O
,	O
instead	O
of	O
having	O
a	O
limited	O
number	O
of	O
low-granularity	O
registers	O
to	O
deal	O
with	O
modern	O
memory	B-General_Concept
sizes	O
that	O
can	O
be	O
as	O
high	O
as	O
64GB	O
even	O
on	O
a	O
laptop	O
,	O
and	O
several	O
times	O
that	O
amount	O
on	O
a	O
desktop	O
system	O
.	O
</s>
<s>
Details	O
on	O
how	O
MTRRs	O
work	O
are	O
described	O
in	O
the	O
processor	O
manuals	O
from	O
CPU	B-Device
vendors	O
.	O
</s>
