<s>
Memory	B-General_Concept
timings	I-General_Concept
or	O
RAM	B-General_Concept
timings	I-General_Concept
describe	O
the	O
timing	O
information	O
of	O
a	O
memory	O
module	O
.	O
</s>
<s>
The	O
timing	O
of	O
modern	O
synchronous	O
dynamic	O
random-access	B-Architecture
memory	I-Architecture
(	O
SDRAM	O
)	O
is	O
commonly	O
indicated	O
using	O
four	O
parameters	O
:	O
CL	O
,	O
TRCD	O
,	O
TRP	O
,	O
and	O
TRAS	O
in	O
units	O
of	O
clock	O
cycles	O
;	O
they	O
are	O
commonly	O
written	O
as	O
four	O
numbers	O
separated	O
with	O
hyphens	O
,	O
e.g.	O
</s>
<s>
These	O
parameters	O
(	O
as	O
part	O
of	O
a	O
larger	O
whole	O
)	O
specify	O
the	O
clock	O
latency	O
of	O
certain	O
specific	O
commands	O
issued	O
to	O
a	O
random	B-Architecture
access	I-Architecture
memory	I-Architecture
.	O
</s>
<s>
When	O
translating	O
memory	B-General_Concept
timings	I-General_Concept
into	O
actual	O
latency	O
,	O
it	O
is	O
important	O
to	O
note	O
that	O
timings	O
are	O
in	O
units	O
of	O
clock	O
cycles	O
,	O
which	O
for	O
double	O
data	O
rate	O
memory	O
is	O
half	O
the	O
speed	O
of	O
the	O
commonly	O
quoted	O
transfer	O
rate	O
.	O
</s>
<s>
With	O
this	O
1ns	O
clock	O
,	O
a	O
CAS	B-Architecture
latency	I-Architecture
of	O
7	O
gives	O
an	O
absolute	O
CAS	B-Architecture
latency	I-Architecture
of	O
7ns	O
.	O
</s>
<s>
Faster	O
DDR3-2666	O
memory	O
(	O
with	O
a	O
1333MHz	O
clock	O
,	O
or	O
0.75ns	O
per	O
cycle	O
)	O
may	O
have	O
a	O
larger	O
CAS	B-Architecture
latency	I-Architecture
of	O
9	O
,	O
but	O
at	O
a	O
clock	O
frequency	O
of	O
1333MHz	O
the	O
amount	O
of	O
time	O
to	O
wait	O
9	O
clock	O
cycles	O
is	O
only	O
6.75ns	O
.	O
</s>
<s>
It	O
is	O
for	O
this	O
reason	O
that	O
DDR3-2666	O
CL9	O
has	O
a	O
smaller	O
absolute	O
CAS	B-Architecture
latency	I-Architecture
than	O
DDR3-2000	O
CL7	O
memory	O
.	O
</s>
<s>
The	O
full	O
memory	B-General_Concept
timings	I-General_Concept
of	O
a	O
memory	O
module	O
are	O
stored	O
inside	O
of	O
a	O
module	O
's	O
SPD	B-General_Concept
chip	O
.	O
</s>
<s>
On	O
DDR3	O
and	O
DDR4	O
DIMM	B-General_Concept
modules	O
,	O
this	O
chip	O
is	O
a	O
PROM	B-General_Concept
or	O
EEPROM	B-General_Concept
flash	O
memory	O
chip	O
and	O
contains	O
the	O
JEDEC-standardized	O
timing	O
table	O
data	O
format	O
.	O
</s>
<s>
See	O
the	O
SPD	B-General_Concept
article	O
for	O
the	O
table	O
layout	O
among	O
different	O
versions	O
of	O
DDR	O
and	O
examples	O
of	O
other	O
memory	B-General_Concept
timing	I-General_Concept
information	O
that	O
is	O
present	O
on	O
these	O
chips	O
.	O
</s>
<s>
Modern	O
DIMMs	B-General_Concept
include	O
a	O
Serial	B-General_Concept
Presence	I-General_Concept
Detect	I-General_Concept
(	O
SPD	B-General_Concept
)	O
ROM	O
chip	O
that	O
contains	O
recommended	O
memory	B-General_Concept
timings	I-General_Concept
for	O
automatic	O
configuration	O
as	O
well	O
as	O
XMP	O
profiles	O
of	O
faster	O
timing	O
information	O
(	O
and	O
higher	O
voltages	O
)	O
to	O
allow	O
a	O
quick	O
and	O
easy	O
performance	O
boost	O
via	O
overclocking	O
.	O
</s>
<s>
The	O
BIOS	B-Operating_System
on	O
a	O
PC	O
may	O
allow	O
the	O
user	O
to	O
manually	O
make	O
timing	O
adjustments	O
in	O
an	O
effort	O
to	O
increase	O
performance	O
(	O
with	O
possible	O
risk	O
of	O
decreased	O
stability	O
)	O
or	O
,	O
in	O
some	O
cases	O
,	O
to	O
increase	O
stability	O
(	O
by	O
using	O
suggested	O
timings	O
)	O
.	O
</s>
<s>
Note	O
:	O
Memory	B-General_Concept
bandwidth	I-General_Concept
measures	O
the	O
throughput	O
of	O
memory	O
,	O
and	O
is	O
generally	O
limited	O
by	O
the	O
transfer	O
rate	O
,	O
not	O
latency	O
.	O
</s>
<s>
By	O
interleaving	B-General_Concept
access	O
to	O
SDRAM	O
's	O
multiple	O
internal	O
banks	O
,	O
it	O
is	O
possible	O
to	O
transfer	O
data	O
continuously	O
at	O
the	O
peak	O
transfer	O
rate	O
.	O
</s>
<s>
Increasing	O
memory	B-General_Concept
bandwidth	I-General_Concept
,	O
even	O
while	O
increasing	O
memory	O
latency	O
,	O
may	O
improve	O
the	O
performance	O
of	O
a	O
computer	O
system	O
with	O
multiple	O
processors	O
and/or	O
multiple	O
execution	O
threads	O
.	O
</s>
<s>
Higher	O
bandwidth	O
will	O
also	O
boost	O
performance	O
of	O
integrated	O
graphics	O
processors	O
that	O
have	O
no	O
dedicated	O
video	O
memory	O
but	O
use	O
regular	O
RAM	B-Architecture
as	O
VRAM	O
.	O
</s>
<s>
Modern	O
x86	B-Operating_System
processors	O
are	O
heavily	O
optimized	O
with	O
techniques	O
such	O
as	O
instruction	B-General_Concept
pipelines	I-General_Concept
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
memory	B-General_Concept
prefetching	I-General_Concept
,	O
memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
,	O
and	O
branch	B-General_Concept
prediction	I-General_Concept
to	O
preemptively	B-Operating_System
load	O
memory	O
from	O
RAM	B-Architecture
(	O
and	O
other	O
caches	O
)	O
to	O
speed	O
up	O
execution	O
even	O
further	O
.	O
</s>
<s>
With	O
this	O
amount	O
of	O
complexity	O
from	O
performance	O
optimization	O
,	O
it	O
is	O
difficult	O
to	O
state	O
with	O
certainty	O
the	O
effects	O
memory	B-General_Concept
timings	I-General_Concept
may	O
have	O
on	O
performance	O
.	O
</s>
<s>
Different	O
workloads	O
have	O
different	O
memory	O
access	O
patterns	O
and	O
are	O
affected	O
differently	O
in	O
performance	O
by	O
these	O
memory	B-General_Concept
timings	I-General_Concept
.	O
</s>
<s>
In	O
Intel	O
systems	O
,	O
memory	B-General_Concept
timings	I-General_Concept
and	O
management	O
are	O
handled	O
by	O
the	O
Memory	B-Device
Reference	I-Device
Code	I-Device
(	O
MRC	O
)	O
,	O
a	O
part	O
of	O
the	O
BIOS	B-Operating_System
.	O
</s>
