<s>
Memory	B-General_Concept
refresh	I-General_Concept
is	O
the	O
process	O
of	O
periodically	O
reading	O
information	O
from	O
an	O
area	O
of	O
computer	B-General_Concept
memory	I-General_Concept
and	O
immediately	O
rewriting	O
the	O
read	O
information	O
to	O
the	O
same	O
area	O
without	O
modification	O
,	O
for	O
the	O
purpose	O
of	O
preserving	O
the	O
information	O
.	O
</s>
<s>
Memory	B-General_Concept
refresh	I-General_Concept
is	O
a	O
background	O
maintenance	O
process	O
required	O
during	O
the	O
operation	O
of	O
semiconductor	O
dynamic	O
random-access	O
memory	O
(	O
DRAM	O
)	O
,	O
the	O
most	O
widely	O
used	O
type	O
of	O
computer	B-General_Concept
memory	I-General_Concept
,	O
and	O
in	O
fact	O
is	O
the	O
defining	O
characteristic	O
of	O
this	O
class	O
of	O
memory	O
.	O
</s>
<s>
Each	O
memory	B-General_Concept
refresh	I-General_Concept
cycle	I-General_Concept
refreshes	O
a	O
succeeding	O
area	O
of	O
memory	O
cells	O
,	O
thus	O
repeatedly	O
refreshing	O
all	O
the	O
cells	O
in	O
a	O
consecutive	O
cycle	O
.	O
</s>
<s>
Electronic	O
memory	O
that	O
does	O
not	O
require	O
refreshing	O
is	O
available	O
,	O
called	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
(	O
SRAM	O
)	O
.	O
</s>
<s>
SRAM	O
circuits	O
require	O
more	O
area	O
on	O
a	O
chip	O
,	O
because	O
an	O
SRAM	O
memory	O
cell	O
requires	O
four	O
to	O
six	O
transistors	B-Application
,	O
compared	O
to	O
a	O
single	O
transistor	B-Application
and	O
a	O
capacitor	O
for	O
DRAM	O
.	O
</s>
<s>
The	O
need	O
for	O
memory	B-General_Concept
refresh	I-General_Concept
makes	O
DRAM	O
timing	O
and	O
circuits	O
significantly	O
more	O
complicated	O
than	O
SRAM	O
circuits	O
,	O
but	O
the	O
density	O
and	O
cost	O
advantages	O
of	O
DRAM	O
justify	O
this	O
complexity	O
.	O
</s>
<s>
Rather	O
than	O
use	O
the	O
normal	O
read	B-General_Concept
cycle	I-General_Concept
in	O
the	O
refresh	O
process	O
,	O
to	O
save	O
time	O
an	O
abbreviated	O
cycle	O
called	O
a	O
refresh	O
cycle	O
is	O
used	O
.	O
</s>
<s>
The	O
refresh	O
cycle	O
is	O
similar	O
to	O
the	O
read	B-General_Concept
cycle	I-General_Concept
,	O
but	O
executes	O
faster	O
for	O
two	O
reasons	O
:	O
</s>
<s>
Data	O
read	O
from	O
the	O
cells	O
does	O
not	O
need	O
to	O
be	O
fed	O
into	O
the	O
output	O
buffers	O
or	O
the	O
data	B-General_Concept
bus	I-General_Concept
to	O
send	O
to	O
the	O
CPU	O
.	O
</s>
<s>
Although	O
in	O
some	O
early	O
systems	O
the	O
microprocessor	B-Architecture
controlled	O
refresh	O
,	O
with	O
a	O
timer	O
triggering	O
a	O
periodic	O
interrupt	B-Application
that	O
ran	O
a	O
subroutine	O
that	O
performed	O
the	O
refresh	O
,	O
this	O
meant	O
the	O
microprocessor	B-Architecture
could	O
not	O
be	O
paused	O
,	O
single-stepped	O
,	O
or	O
put	O
into	O
energy-saving	O
hibernation	O
without	O
stopping	O
the	O
refresh	O
process	O
and	O
losing	O
the	O
data	O
in	O
memory	O
.	O
</s>
<s>
So	O
in	O
modern	O
systems	O
refresh	O
is	O
handled	O
by	O
circuits	O
in	O
the	O
memory	B-General_Concept
controller	I-General_Concept
,	O
which	O
may	O
be	O
embedded	B-Architecture
in	O
the	O
chip	O
itself	O
.	O
</s>
<s>
Some	O
DRAM	O
chips	O
,	O
such	O
as	O
pseudostatic	O
RAM	O
(	O
PSRAM	O
)	O
,	O
have	O
all	O
the	O
refresh	O
circuitry	O
on	O
the	O
chip	O
,	O
and	O
function	O
like	O
static	B-Architecture
RAM	I-Architecture
as	O
far	O
as	O
the	O
rest	O
of	O
the	O
computer	O
is	O
concerned	O
.	O
</s>
<s>
This	O
counter	O
may	O
be	O
part	O
of	O
the	O
memory	B-General_Concept
controller	I-General_Concept
circuitry	O
,	O
or	O
on	O
the	O
memory	O
chip	O
itself	O
.	O
</s>
<s>
Burst	O
refresh	O
results	O
in	O
long	O
periods	O
when	O
the	O
memory	O
is	O
unavailable	O
,	O
so	O
distributed	O
refresh	O
has	O
been	O
used	O
in	O
most	O
modern	O
systems	O
,	O
particularly	O
in	O
real	B-General_Concept
time	I-General_Concept
systems	O
.	O
</s>
<s>
"	O
RAS	O
only	O
refresh	O
"	O
-	O
In	O
this	O
mode	O
the	O
address	O
of	O
the	O
row	O
to	O
refresh	O
is	O
provided	O
by	O
the	O
address	O
bus	O
lines	O
,	O
so	O
it	O
is	O
used	O
with	O
external	O
counters	O
in	O
the	O
memory	B-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
This	O
improvement	O
is	O
achieved	O
mainly	O
by	O
developing	O
transistors	B-Application
that	O
cause	O
significantly	O
less	O
leakage	O
.	O
</s>
<s>
However	O
transistor	B-Application
leakage	O
currents	O
vary	O
widely	O
between	O
different	O
memory	O
cells	O
on	O
the	O
same	O
chip	O
due	O
to	O
process	O
variation	O
.	O
</s>
<s>
This	O
frequent	O
DRAM	B-General_Concept
refresh	I-General_Concept
consumes	O
a	O
third	O
of	O
the	O
total	O
power	O
drawn	O
by	O
low-power	O
electronics	O
devices	O
in	O
standby	O
mode	O
.	O
</s>
<s>
In	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
(	O
SRAM	O
)	O
,	O
another	O
type	O
of	O
semiconductor	O
memory	O
,	O
the	O
data	O
is	O
not	O
stored	O
as	O
charge	O
on	O
a	O
capacitor	O
,	O
but	O
in	O
a	O
pair	O
of	O
a	O
cross-coupled	O
inverters	O
,	O
so	O
SRAM	O
does	O
not	O
need	O
to	O
be	O
refreshed	O
.	O
</s>
<s>
However	O
,	O
the	O
internal	O
construction	O
of	O
each	O
SRAM	O
cell	O
requires	O
six	O
transistors	B-Application
,	O
compared	O
to	O
the	O
single	O
transistor	B-Application
required	O
for	O
a	O
DRAM	O
cell	O
,	O
so	O
the	O
density	O
of	O
SRAM	O
is	O
much	O
lower	O
and	O
price-per-bit	O
much	O
higher	O
than	O
DRAM	O
.	O
</s>
<s>
Some	O
early	O
microprocessors	B-Architecture
(	O
e.g.	O
</s>
<s>
the	O
Zilog	B-General_Concept
Z80	I-General_Concept
)	O
provided	O
special	O
internal	O
registers	O
that	O
could	O
provide	O
the	O
Row-Address	O
Strobe	O
(	O
RAS	O
)	O
to	O
refresh	O
dynamic	O
memory	O
cells	O
,	O
the	O
register	O
being	O
incremented	O
on	O
each	O
refresh	O
cycle	O
.	O
</s>
<s>
the	O
Motorola	B-General_Concept
6845	I-General_Concept
)	O
.	O
</s>
<s>
In	O
CPUs	O
such	O
as	O
the	O
Z80	B-General_Concept
,	O
the	O
availability	O
of	O
a	O
RAS	O
refresh	O
was	O
a	O
big	O
selling-point	O
due	O
to	O
its	O
simplifying	O
hardware	O
design	O
.	O
</s>
<s>
In	O
early	O
versions	O
of	O
the	O
Z80	B-General_Concept
,	O
the	O
ubiquity	O
of	O
16	O
kB	O
RAM	O
chips	O
(	O
i.e.	O
</s>
<s>
In	O
some	O
contexts	O
,	O
it	O
was	O
possible	O
to	O
utilise	O
interrupts	B-Application
to	O
flip	O
the	O
8th	O
bit	O
at	O
the	O
appropriate	O
time	O
and	O
thus	O
cover	O
the	O
entire	O
range	O
of	O
the	O
R	O
register	O
(	O
256	O
rows	O
)	O
.	O
</s>
<s>
Later	O
versions	O
and	O
licensed	O
"	O
work-alikes	O
"	O
of	O
the	O
Z80	B-General_Concept
core	O
remedied	O
the	O
non-inclusion	O
of	O
the	O
8th	O
bit	O
in	O
automatic	O
cycling	O
,	O
and	O
modern	O
CPUs	O
have	O
greatly	O
expanded	O
on	O
such	O
basic	O
provisioning	O
to	O
provide	O
rich	O
all-in-one	O
solutions	O
for	O
DRAM	B-General_Concept
refresh	I-General_Concept
.	O
</s>
<s>
Pseudostatic	O
RAM	O
(	O
PSRAM	O
or	O
PSDRAM	O
)	O
is	O
dynamic	O
RAM	O
with	O
built-in	O
refresh	O
and	O
address-control	O
circuitry	O
to	O
make	O
it	O
behave	O
similarly	O
to	O
static	B-Architecture
RAM	I-Architecture
(	O
SRAM	O
)	O
.	O
</s>
<s>
PSRAM	O
(	O
made	O
by	O
Numonyx	O
)	O
is	O
used	O
in	O
the	O
Apple	O
iPhone	O
and	O
other	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
An	O
embedded	B-Architecture
variant	O
of	O
PSRAM	O
is	O
sold	O
by	O
MoSys	O
under	O
the	O
name	O
1T-SRAM	O
.	O
</s>
<s>
It	O
is	O
technically	O
DRAM	O
,	O
but	O
behaves	O
much	O
like	O
SRAM	O
,	O
and	O
is	O
used	O
in	O
the	O
GameCube	B-Application
and	O
Wii	B-Operating_System
consoles	I-Operating_System
.	O
</s>
<s>
Several	O
early	O
computer	B-General_Concept
memory	I-General_Concept
technologies	O
also	O
required	O
periodical	O
processes	O
similar	O
in	O
purpose	O
to	O
the	O
memory	O
refreshing	O
.	O
</s>
<s>
The	O
Williams	B-General_Concept
tube	I-General_Concept
has	O
the	O
closest	O
similarity	O
,	O
since	O
,	O
as	O
with	O
DRAM	O
,	O
it	O
is	O
essentially	O
a	O
capacitive	O
memory	O
in	O
which	O
the	O
values	O
stored	O
for	O
each	O
bit	O
would	O
gradually	O
decay	O
unless	O
refreshed	O
.	O
</s>
<s>
As	O
a	O
consequence	O
,	O
the	O
memory	B-General_Concept
controller	I-General_Concept
typically	O
added	O
a	O
refresh	O
cycle	O
after	O
each	O
read	B-General_Concept
cycle	I-General_Concept
in	O
order	O
to	O
create	O
the	O
illusion	O
of	O
a	O
non-destructive	O
read	O
operation	O
.	O
</s>
<s>
In	O
this	O
case	O
,	O
the	O
refresh	O
rate	O
is	O
comparable	O
to	O
the	O
memory	O
access	B-General_Concept
time	I-General_Concept
.	O
</s>
